UPD30121 datasheet(12/76 Pages) NEC

12 / 76 page

Data Sheet U14691EJ1V0DS00

µµµµPD30121

(5)

RS-232C interface signals

Signal

I/O

Function

RxD

This is a receive data signal. It is used when the RS-232C controller sends serial data to the VR4121.

CTS#

This is a transmit enable signal. Assert this signal when the RS-232C controller is ready to receive

transmission of serial data.

DCD#/

GPIO15

This is a carrier detection signal. Assert this signal when valid serial data is being received. It is also

used when detecting a power-on factor for the VR4121.

When this pin is not used for DCD# signal, this pin can be used as an interrupt detection function for the

GIU unit.

DSR#

This is the data set ready signal. Assert this signal when the RS-232C controller is ready to

receive/transmit serial data between the controller and the VR4121.

TxD/

CLKSEL2,

RTS#/

CLKSEL1,

DTR#/

CLKSEL0

I/O

This function differs depending on the operating status.

Signals used for serial communication

TxD signal :

This is a transmit data signal. It is used when the VR4121 sends serial data to the RS-232C

controller.

RTS# signal :

This is a transmit request signal. This signal is asserted when the VR4121 is ready to receive serial

data from the RS-232C controller.

DTR# signal :

This is a terminal equipment ready signal. This signal is asserted when the VR4121 is ready to

transmit or receive serial data.

Signals (CLKSEL (2:0) signal) used to set the CPU core operation frequency, BUSCLK signal

frequency, and internal bus clock frequency. These signals are sampled when the RTCRST# signal

changes from low level to high level.

The relationships between the CLKSEL (2:0) signal setting and each clock frequency are shown below.

Notes 1. Do not set CLKSEL (2:0) = 111.

2. The settings CLKSEL (2:0) = 110 and 101 are only guaranteed for the 168 MHz model. Do not apply

these settings to the 131 MHz model.

SDRAM/SROM

operation frequency

(VTClock)

CLKSEL

(2:0)

signal

CPU core

operation

frequency

(PClock)

MIN.

MAX.

BUSCLK

signal

frequency

(When

TClock

output)

BUSCLK

signal

requency

(When 1/4

of TClock)

Interrupt

control

clock

frequency

(MasterOut)

111

Note 1

RFU

110

Note 2

168.5 MHz

28.1 MHz

56.2 MHz

28.1 MHz

7.0 MHz

101

Note 2

147.5 MHz

29.5 MHz

59.0 MHz

29.5 MHz

7.4 MHz

100

131.1 MHz

32.8 MHz

65.5 MHz

32.8 MHz

8.2 MHz

011

118.0 MHz

29.5 MHz

59.0 MHz

29.5 MHz

7.4 MHz

010

98.3 MHz

32.8 MHz

65.5 MHz

32.8 MHz

8.2 MHz

001

90.7 MHz

30.2 MHz

60.5 MHz

30.2 MHz

7.6 MHz

000

78.6 MHz

26.2 MHz

52.4 MHz

26.2 MHz

6.6 MHz

UPD30121 데이터시트(PDF) 12 Page - NEC

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