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PM0222

Timers

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See Brain reference manual, Dual timer module chapter, Register descriptions sub-chapter

for more details.

// timer configuration, after this command the timer is launched.

DUALTIMER0->Timer1Control = 0xE3

Every 8388608 (0x800000) tick periods the timer will reach zero and generate an interrupt.

The Timer1Value register contains the current value of the timer. It can be read at any

moment when the timer is running.

current = DUALTIMER0->Timer1Value; // save current timer value.

8.1.2

One-shot mode

// disable the timer1 of dual-timer0, and all previous configurations in case of a

// previous use.

DUALTIMER0->Timer1Control = 0x00;

DUALTIMER0->Timer1Load = 0x800000; // load a new timer value

Then to launch the timer, the Timer1Control register has to be configured. In this example

the timer1 configuration is:



32-bit mode



No division on timer1 incoming clock



Interrupt is enabled for timer1



One-shot mode and timer1 are enabled.

See Brain reference manual, Dual timer module chapter, Register descriptions sub-chapter

for more details.

// timer configuration, after this command the timer is launched.

DUALTIMER0->Timer1Control = 0xE2

After 8388608 (0x800000) tick periods the timer will reach zero and generate an interrupt.

The Timer1Value register contains the current value of the timer. It can be read at any

moment when the timer is running.

current = DUALTIMER0->Timer1Value;// save current timer value

At this stage, writing a new value in the Timer1Load register will restart the timer1 with this

new value and stop again when it reaches zero.

At any moment in both configurations the timer1 can be stopped by writing 0x00 in the

Timer1Control register.

8.2

Watchdog (WDG)

All watchdog registers are described in a structure defined in the Brain header file (.h)

provided by STMicroelectronics.

The watchdog APB base address: 0xAA00_0000

The watchdog timer is clocked by the 32 kHz clock.

The watchdog peripheral clock should be enabled on the CRMU side (see Section 3.1:

Peripheral clock gating) and the corresponding interrupt should be enabled on the Cortex-