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This sequence will trigger a master write operation of one data present in the transmit FIFO

to a slave I²C device addressed by 0x1D. The I2C_SR register contains information

concerning the status of the transaction:



Operation type (master-read, master-write, write-to-slave and read-from-slave).



Status (successful, abort)



Cause of the abort



Length of the transaction

This information will help to determine the next operation. For example, in case of an abort

status, the program may retry starting the transaction.

10.3.2

I²C slave

address 0x1E.

// mode for the baud rate generation

I2C2->I2C_CR = 0x01 + (0x0<<1) + (0x0<<3) + (0x1<<4)

I2C2->I2C_SCR = 0x1E; // define the slave address

After this configuration the I2C2 is ready to work as a slave. Check the I2C_SR register to

get the status of the transaction (see Section 10.3.1: I2C master).

10.4

10.4.1

I2C2

The first bit of the I2C_CONF register (see Brain reference manual, GPIO chapter) is used

to reroute the I2C2 pins. After reset, this bit is configured as one, which means the I2C2 pins

are rerouted through MCL and MDA, specific open-drain I/Os. If this bit is set to zero, the

I2C2 pins are rerouted to digital standard push-pull I/Os. In both configurations, IO7 and IO8

have to be in serial mode 0 (see Section 5.1.1: I/O mode) to access the I2C2 pins,

according to the configuration of the I2C_CONF register.