SPI

PM0222

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11.3

SPI configuration

Following a reset, the SPI logic is disabled and must be configured when in this state.

Control registers SSPCR0 and SSPCR1 need to be programmed to configure the peripheral

as a master or slave operating under one of the following protocols:



Motorola SPI



Texas Instruments SSI



National semiconductor Microwire

The bit rate is programmed in the clock prescale register SSPCPSR. All details about these

three protocols can be found in “ARM PrimeCell® Synchronous Serial Port (PL022)

Technical Reference Manual”.

The SSPCR0 is used to:



Program the serial clock rate



Select one of the three protocols



Select the data word size

The SSPCR1 is used to:



Select the master or slave mode



Enable a loop-back test feature



Enable the SPI peripheral

Before using these examples, the SPI module has to be enabled on the CRMU (see

Section 3.1: Peripheral clock gating). Furthermore, the correct mode has to be configured

for the corresponding IO (see Section 5.1.1: I/O mode).

11.3.1

Master SPI

This section will show an example of configuring the SPI IP in Motorola master mode with bit

phase and polarity (only for Motorola protocol) to zero (see Brain reference manual, SPI

chapter for more details), 16-bit data size and a bit rate defined by the processor clock

divided by two.

// SCR to zero, Motorola protocol, bit phase to zero, polarity to zero and 16-bit data

// transfer.

SPI1->SSPCR0 = 0x0<<8 | 0x0<<7 | 0x0<<6 | 0x00<<4 | 0xF

// select the master mode and enable the SPI

SPI1->SSPCR1 = 0x0<<2 | 0x1<<1

// CPSDVR to two. The bit rate will be the SPI clock (processor clock) divided by two.

SPI1->SSPCPSR = 0x2

After this configuration the SPI is ready to work as a master. A write to the transmit FIFO

through the SSPDR register will trigger a transaction. At the end of the transaction, the

received data is available by reading the SSPDR register.