UART

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9.3

Basic configuration

Before using the previous examples, the UART module has to be enabled in the CRMU

(see Section 3.1: Peripheral clock gating) and the correct mode has to be configured for the

corresponding IO (see Section 5.1.1: I/O mode).

There are four important registers:



UARTIBRD and UARTFBRD to configure the baud rate (see Section 9.2: Baud rate

calculation example or Brain reference manual, UART chapter, UARTFBRD register

description for more details)



UARTLCR_H to define the data size



UARTCR to enable the IP and the transmitter and receiver mode (both modes can be

enabled at the same time). A write to the transmit FIFO through the UARTDR register

triggers a transaction. A read from the receive FIFO through the UARTDR will return

the first data received.

This sequence below shows how to configure the UART to put it in receiver and transmitter

mode:

UART->UARTCR &= 0xFE; // disable the UART

UART-> UARTLCR_H &= 0x7; // disable and flush the FIFOs

UART->UARTCR |= 0x300; // UART in receiver and transmitter mode

UART-> UARTLCR_H |= 0x8; // enable the FIFOs

UART-> UARTLCR_H |= 0x60; // data transfer of 8 bits

UART->UARTIBRD = 0x1; // UART baud rate configuration, integer part

UART->UARTFBRD = 0x5; // UART baud rate configuration, fractional part

UART->UARTCR |= 0x1; // enable the UART

After this configuration the UART is able to work as a receiver and a transmitter, generating

a specific baud rate (see Section 9.2: Baud rate calculation example). To manage data

transfer, the UARTFR register contains a status bit concerning FIFO. A simple configuration

for a data transmission is:

- Wait until the UART busy flag (BUSY) goes low

- Write in the transmit FIFO to trigger the transaction and send data.