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PM0222

SPI

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11

SPI

All SPI registers are described in a structure defined in the Brain header file (.h) provided by

STMicroelectronics.

Brain has one SPI available at the following address in the memory map:

SPI APB base address: 0xA300_0000

11.1

FIFO management

The transmit and receive paths are buffered with internal FIFO memory enabling up to 16

bytes to be stored independently in both transmit and receive modes..

FIFO status can be checked using the SSPSR register. It contains status about full/empty

FIFO conditions. There are also two interrupts which can be set when the transmit FIFO is

half empty and when the receive FIFO is half full. This set of information is useful to manage

large data transfers.

11.2

Clock rate calculation example

There are two fields that define the SPI baud rate: the SCR field in the SSPCR0 register and

the CPSDVR field in the SSPCPSR register.

We can calculate the clock rate using this formula:

Clock rate = FSSPCLK / (CPSDVR x ( SCR + 1 ) )

where:



FSSPCLK is the SPI reference clock frequency, clocked on the processor clock (see

Brain reference manual, Clock and reset management unit chapter)



CPSDVR is an even value from 2-254 programmed in the SSPCPSR register



SCR is a value from 0-255 programmed in the SSPCR0 register

Example: programming a clock rate

If the FSSPCLK = 16 MHz and the CPSDVR = 2 then:

the clock rate has a frequency range from 8 MHz (SCR = 0) to 31.25 kHz (SCR = 255).

Note:

In master mode the processor clock frequency must be at least two times bigger than the

SPI clock rate.

Note:

In slave mode the clock rate must be twelve times smaller than the processor clock

frequency to guarantee the data transfer.