Peripheral migration guide

AN4658

16/24

DocID027496 Rev 1

The added bits in PWR_CR and PWR_CSR registers are shown in Table 11 and Table 12,

respectively: the new features are highlighted in red, while blue indicates same feature with

specification change or enhancement. Reserved bits are in light gray.

Table 11. PWR_CR register for STM32F446xx products

Table 12. PWR_CSR register for STM32F446xx products

2.9

U(S)ART

The STM32F446 includes the Same USART interface used in the STM32F429/439, as

indicated in Table 13.

2.10

I2C

The STM32F446xx implements exactly the same features on the I2C interface (I2C1, I2C2

and I2C3) as the STM32F429xx/439xx.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

FISSR FMSSR

UDEN[1:0]

ODSWEN ODEN

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VOS[1:0]

ADCDC1

Res.

MRUDS LPUDS

FPDS

DBP

PLS[2:0]

PVDE

CSBF

CWUF

PDDS

LPDS

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

UDRDY[1:0]

ODSWRDY ODRDY

15

14

13

12

11

10

9

8

7

654

3

2

1

0

Res.

VOSRDY

Res.

Res.

Res.

Res.

BRE

Res.

Res.

Res.

BRR

PVDO

SBF

WUF

Table 13. USART comparison

U(S)ART

STM32F429xx/439xx

STM32F446xx

UART/USART

4 / 4

4 / 2

Baudrate

up to 4x11.25 Mbit/s

Clock

Single clock domain

Data

Word length: programmable (8 or 9 bits)

Interrupt

10 interrupt sources with flags

Features

LIN mode

SPI Master

IrDA SIR ENDEC block

Hardware flow control (CTS/RTS)

Continuous communication using DMA

Multiprocessor communication

Single-wire half-duplex communication