UPD750064CU datasheet(40/82 Pages) NEC

40 / 82 page

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Data Sheet U10165EJ2V0DS00

Table 9-1. Status of Each Hardware After Reset (2/2)

Hardware

RESET Signal Generation

in Standby Mode

in Operation

Serial interface

Shift register (SIO)

Held

Undefined

Operation mode register (CSIM)

SBI control register (SBIC)

Clock generator,

Processor clock control register (PCC)

clock output

System clock control register (SCC)

circuit

Clock output mode register (CLOM)

Sub-oscillator control register (SOS)

A/D converter

Mode register (ADM)

04H

SA register (SA)

7FH

Interrupt

Interrupt request flag (IRQ

×××)

Reset (0)

function

Interrupt enable flag (IE

×××)0

Interrupt priority selection register (IPS)

INT0, 1, 2 mode registers (IM0, IM1, IM2)

0, 0, 0

Digital port

Output buffer

Off

Output latch

Cleared (0)

I/O mode registers (PMGA, PMGB)

Pull-up resistor setting register (POGA)

Bit sequential buffer (BSB0 to BSB3)

Held

Undefined

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