LAN9500AI datasheet(94/213 Pages) MICROCHIP

94 / 213 page

LAN950x

DS00001875A-page 94

 2010 - 2015 Microchip Technology Inc.

5.8

Customized Operation Without EEPROM

Customized operation without EEPROM is supported only by LAN9500A/LAN9500Ai.

The device provides the capability to customize operation without the use of an EEPROM. Descriptor information and

initialization quantities normally fetched from EEPROM and used to initialize descriptors and elements of the System

Control and Status Registers may be specified via an alternate mechanism. This alternate mechanism involves the use

of the Descriptor RAM in conjunction with the Attribute Registers and select elements of the System Control and Status

Registers. The software device driver orchestrates the process by performing the following actions in the order indi-

cated:

• Initialization of SCSR Elements in Lieu of EEPROM Load

• Attribute Register Initialization

• Descriptor RAM Initialization

• Enable Descriptor RAM and Flag Attribute Registers as Source

• Inhibit Reset of Select SCSR Elements

The following subsections explain these actions. The attribute registers must be written prior to initializing the Descriptor

RAM. Failure to do this will prevent the PWR_SEL and RMT_WKUP flags from being overwritten by the bmAttributes

of the Configuration Descriptor.

5.8.1

INITIALIZATION OF SCSR ELEMENTS IN LIEU OF EEPROM LOAD

During EEPROM operation, the following register fields are initialized by the hardware using the values contained in the

EEPROM. In the absence of an EEPROM, the software device driver must initialize these quantities:

• MAC Address High Register (ADDRH) and MAC Address Low Register (ADDRL)

• PHY Boost (PHY_BOOST) field of Hardware Configuration Register (HW_CFG)

• LED Select (LED_SEL) bit of the LED General Purpose IO Configuration Register (LED_GPIO_CFG)

• GPIO Wake 0-10 (GPIOWKn) field of the General Purpose IO Wake Enable and Polarity Register (GPIO_WAKE)

5.8.2

ATTRIBUTE REGISTER INITIALIZATION

The Attribute Registers are as follows:

• HS Descriptor Attributes Register (HS_ATTR)

• FS Descriptor Attributes Register (FS_ATTR)

• String Descriptor Attributes Register 0 (STRNG_ATTR0)

• String Descriptor Attributes Register 1 (STRNG_ATTR1)

• Flag Attributes Register (FLAG_ATTR)

All of these registers, with the exception of FLAG_ATTR, contain fields defining the lengths of the descriptors written

into the Descriptor RAM. If the descriptor is not written into the Descriptor RAM, the associated entry in the Attributes

results.

90h

Value used to select alternative setting

91h

Number of Endpoints used for this interface (Less endpoint 0)

92h

Class Code

93h

Subclass Code

94h

Protocol Code

95h

Index of String Descriptor Describing this interface

96h - FFh

Data storage for use by Host as desired

TABLE 5-65:

EEPROM EXAMPLE - 256 BYTE EEPROM - LAN9500A/LAN9500AI (CONTINUED)

EEPROM

Address

EEPROM Contents

(Hex)

Description

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