LAN9500AI datasheet(13/213 Pages) MICROCHIP

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DS00001875A-page 13

LAN950x

MII Collision

Detect

(Internal PHY

Mode)

COL

IS/O8

(PU)

In internal PHY mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 122 for additional information.

MII Collision

Detect

(External PHY

Mode)

COL

(PD)

In external PHY mode, the signal on this pin is

input from the external PHY and indicates a

collision event.

General

Purpose I/O 0

(Internal PHY

Mode Only)

GPIO0

IS/O8/

OD8

(PU)

This General Purpose I/O pin is fully

programmable as either a push-pull output, an

open-drain output, or a Schmitt-triggered input.

Note:

(LAN9500A/LAN9500Ai ONLY):

This pin may be used to signal PME

when Internal PHY and PME modes of

operation are in effect. Refer to Section

6.0, "PME Operation," on page 112 for

additional information.

Management

Data

(Internal PHY

Mode)

MDIO

IS/O8

(PU)

In internal PHY mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 122 for additional information.

Management

Data

(External PHY

Mode)

MDIO

IS/O8

(PD)

In external PHY mode, this pin provides the

management data to/from the external PHY.

General

Purpose I/O 1

(Internal PHY

Mode Only)

GPIO1

IS/O8/

OD8

(PU)

This General Purpose I/O pin is fully

programmable as either a push-pull output, an

open-drain output, or a Schmitt-triggered input.

Note:

(LAN9500A/LAN9500Ai ONLY):

This pin may serve as the

PME_MODE_SEL input when Internal

PHY and PME modes of operation are in

effect. Refer to Section 6.0, "PME

Operation," on page 112 for additional

information.

Management

Clock

(Internal PHY

Mode)

MDC

IS/O8

(PU)

In internal PHY mode, this pin can be configured

to display the respective internal MII signal. Refer

to the Internal MII Visibility Enable (IME) bit of the

Hardware Configuration Register (HW_CFG) on

page 122 for additional information.

Management

Clock

(External PHY

Mode)

MDC

(PD)

In external PHY mode, this pin outputs the

management clock to the external PHY.

General

Purpose I/O 2

(Internal PHY

Mode Only)

GPIO2

IS/O8/

OD8

(PU)

This General Purpose I/O pin is fully

programmable as either a push-pull output, an

open-drain output, or a Schmitt-triggered input.

TABLE 3-1:

MII INTERFACE PINS (CONTINUED)

Num Pins

Name

Symbol

Buffer

Type

Description

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