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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LAN9500AI 데이터시트(PDF) 141 Page - Microchip Technology |
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LAN9500AI 데이터시트(HTML) 141 Page - Microchip Technology |
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141 / 213 page  2010 - 2015 Microchip Technology Inc. DS00001875A-page 141 LAN950x 7.3.15 DATA PORT SELECT REGISTER (DP_SEL) Before accessing the internal RAMs, the TESTEN bit must be set. It is not valid to use the RAM data port during run time. The RAM Test Mode Select chooses which internal RAM to access. The Data Port Ready bit indicates when the data port RAM access has completed. In the case of a read operation, this indicates when the read data has been stored in the DP_DATA register. Address: 040h Size: 32 bits Bits Description Type Default 31 Data Port Ready (DPRDY) 0 = data port is busy processing a transaction 1 = data port is ready RO 1b 30:3 RESERVED RO - 2:1 RAM Test Select (RSEL) Selects which RAM to access. 00 = FCT Data RAM 01 = EEPROM storage RAM 10 = TX TLI RAM 11 = RX TLI RAM R/W 0b 0 RAM Test Mode Enable (TESTEN) Put all test accessible RAMs in test mode. R/W 0b |
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