MEC1322 datasheet(153/456 Pages) MICROCHIP

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 2014 - 2015 Microchip Technology Inc.

DS00001719D-page 153

MEC1322

11.13.1

ACTIVATE REGISTER

11.14 Runtime Registers

The registers listed in the Runtime Register Summary table are for a single instance of the Emulated 8042 Interface.

The addresses of each register listed in this table are defined as a relative offset to the host “Base Address” defined in

the Runtime Register Base Address Table.

The Base Address indicates where the first register can be accessed in a particular address space for a block instance.

11.14.1

HOST_EC DATA / CMD REGISTER

Offset

30h

Bits

Description

Type

Default

Reset

Event

7:1 Reserved

0ACTIVATE

1=The 8042 Interface is powered and functional.

0=The 8042 Interface is powered down and inactive.

R/W

PWRGD

and

VCC1_R

ESET

Block Instance

Instance Number

Host

Address Space

Base Address

Emulated 8042

Interface

LPC

I/O

Programmed BAR

32-bit address

space

400F_0400h

TABLE 11-12: RUNTIME REGISTER SUMMARY

Offset

00h/04h

HOST_EC Data / CMD Register

00h

EC_HOST Data / AUX Data Register

04h

Keyboard Status Read Register

Offset

00h

Bits

Description

Type

Default

Reset

Event

7:0 WRITE_DATA

This 8-bit register is write-only. When written, the C/D bit in the Key-

board Status Read Register is cleared to ‘0’, signifying data, and the

IBF in the same register is set to ‘1’.

When the Runtime Register at offset 0h is read by the Host, it func-

tions as the EC_HOST Data / AUX Data Register.

W0h

VCC1_R

ESET

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