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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MEC1322 데이터시트(PDF) 154 Page - Microchip Technology |
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MEC1322 데이터시트(HTML) 154 Page - Microchip Technology |
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154 / 456 page  MEC1322 DS00001719D-page 154 2014 - 2015 Microchip Technology Inc. 11.14.2 EC_HOST DATA / AUX DATA REGISTER 11.14.3 KEYBOARD STATUS READ REGISTER This register is a read-only alias of the EC Keyboard Status Register. Offset 04h Bits Description Type Default Reset Event 7:0 WRITE_CMD This 8-bit register is write-only and is an alias of the register at offset 0h. When written, the C/D bit in the Keyboard Status Read Register is set to ‘1’, signifying a command, and the IBF in the same register is set to ‘1’. When the Runtime Register at offset 4h is read by the Host, it func- tions as the Keyboard Status Read Register. W0h VCC1_R ESET Offset 00h Bits Description Type Default Reset Event 7:0 READ_DATA This 8-bit register is read-only. When read by the Host, the PCOBF and/or AUXOBF interrupts are cleared and the OBF flag in the status register is cleared. R0h VCC1_R ESET Offset 04h Bits Description Type Default Reset Event 7:6 UD2 User-defined data. Readable and writable by the EC when written by the EC at its EC-only alias. R0h VCC1_R ESET 5AUXOBF Auxiliary Output Buffer Full. This bit is set to “1” whenever the EC writes the EC AUX Data Register. This flag is reset to “0” whenever the EC writes the EC Data Register. R0h VCC1_R ESET 4 UD1 User-defined data. Readable and writable by the EC when written by the EC at its EC-only alias. R0h VCC1_R ESET 3C/D Command Data. This bit specifies whether the input data register contains data or a command (“0” = data, “1” = command). During a Host command write operation (when the Host writes the HOST_EC Data / CMD Register at offset 04h), this bit is set to “1”. During a Host data write operation (when the Host writes the HOST_EC Data / CMD Register at offset 0h), this bit is set to “0”. R0h VCC1_R ESET 2 UD0 User-defined data. Readable and writable by the EC when written by the EC at its EC-only alias. Note: This bit is reset to ‘0’ when the LRESET# pin signal is asserted. R0h VCC1_R ESET and PCI RESET# |
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