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AD6679 데이터시트(PDF) 36 Page - Analog Devices

부품명 AD6679
상세설명  135 MHz BW IF Diversity Receiver
PDF  81 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD6679 데이터시트(HTML) 36 Page - Analog Devices

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AD6679
Data Sheet
Rev. B | Page 36 of 81
VIRTUAL CONVERTER MAPPING
The AD6679 contains a configurable signal path that allows
different features to be enabled for different applications. These
features are controlled through the chip application mode
register (0x200). The chip operating mode is controlled by
Bits[3:0] and the Chip Q ignore is controlled by Bit 5.
The AD6679 contains the following digital features:
•
Two analog-to-digital converter (ADC) cores
•
Four digital downconverter (DDC) channels
•
Two noise shaped requantizer (NSR) blocks with optional
decimate by two blocks
•
Two variable dynamic range (VDR) blocks
After the chip application mode has been selected, the output
decimation ratio is set using the chip decimation ratio in
Register 0x201, Bits[2:0]. The output sample rate is the ADC
sample rate divided by the chip decimation ratio.
To support the different application layer modes, the AD6679
treats each sample stream (real or I or Q) as originating from
separate virtual converters. Table 12 shows the number of
virtual converters required for each chip mode.
The AD6679 supports up to four digital DDC blocks. Each
DDC block outputs either two sample streams (I/Q) for the
complex data components (real + imaginary) or one sample
stream for real (I) data. The AD6679 can be configured to use up
to eight virtual converters depending on the DDC configuration.
Figure 60 shows the virtual converters and their relationship to
DDC outputs when complex outputs are used.
Table 12 shows the virtual converter mapping for each chip
operating mode when channel swapping is disabled.
Table 12. Virtual Converter Mapping
No. of
Virtual
Converters
Supported
Chip
Operating
Mode
(Register
0x200[3:0])
Chip Q
Ignore
(Register
0x200[5])
Virtual Converter Mapping1
0
1
2
3
4
5
6
7
1
One DDC
mode (0x1)
Real
(I only)
(0x1)
DDC 0
I samples
N/A
N/A
N/A
N/A
N/A
N/A
N/A
2
One DDC
mode (0x1)
Complex
(I/Q)
(0x0)
DDC 0
I samples
DDC 0
Q samples
N/A
N/A
N/A
N/A
N/A
N/A
2
Two DDC
mode (0x2)
Real
(I only)
(0x1)
DDC 0
I samples
DDC 1
I samples
N/A
N/A
N/A
N/A
N/A
N/A
4
Two DDC
mode (0x2)
Complex
(I/Q)
(0x0)
DDC 0
I samples
DDC 0
Q samples
DDC 1
I samples
DDC 1
Q samples
N/A
N/A
N/A
N/A
4
Four DDC
mode (0x3)
Real
(I only)
(0x1)
DDC 0
I samples
DDC 1
I samples
DDC 2
I samples
DDC 3
I samples
N/A
N/A
N/A
N/A
8
Four DDC
mode (0x3)
Complex
(I/Q)
(0x0)
DDC 0
I samples
DDC 0
Q samples
DDC 1
I samples
DDC 1
Q samples
DDC 2
I samples
DDC 2
Q samples
DDC 3
I samples
DDC 3
Q samples
1 to 2
NSR mode
(0x7)
Real or
complex
(0x0)
ADC A
samples
ADC B
samples
N/A
N/A
N/A
N/A
N/A
N/A
1 to 2
VDR mode
(0x8)
Real or
complex
(0x0)
ADC A
samples
ADC B
samples
N/A
N/A
N/A
N/A
N/A
N/A
1
N/A means not applicable.



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