Data Sheet

AD9652

SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD3 = 3.3 V, AVDD = AVDD_CLK = 1.8 V, SPIVDD = DRVDD = 1.8 V, sample rate = 310 MSPS (clock input = 1240 MHz, AD9652

divided by 4), VIN = −1.0 dBFS differential input, 2.5 V p-p full-scale input range, duty cycle stabilizer (DCS) enabled, dither disabled,

unless otherwise noted.

Table 1.

Parameter

Temperature

Min

Typ

Max

Unit

RESOLUTION

Full

16

Bits

ACCURACY

No Missing Codes

Full

Guaranteed

Offset Error

Full

1.5

mV

Gain Error

Full

−0.3

% FSR

Differential Nonlinearity (DNL) 1

Full

−0.76/+1.1

LSB

Integral Nonlinearity (INL)1

Full

−4.5/+4.5

LSB

MATCHING CHARACTERISTIC

Offset Error

Full

±0.7

mV

Gain Error

Full

±0.1

%FSR

TEMPERATURE DRIFT

Offset Error

Full

±0.8

ppm/°C

Gain Error

Full

±16

ppm/°C

INPUT REFERRED NOISE

25°C

3.7

LSB rms

ANALOG INPUT

Full

2.5

V p-p

Input Capacitance2

Full

5.8

pF

Input Resistance3

Full

27

kΩ

Input Common-Mode Voltage

Full

2.0

2.4

V

POWER SUPPLIES

Supply Voltage

AVDD3

Full

3.15

3.3

3.45

V

AVDD

Full

1.7

1.8

1.9

V

AVDD_CLK

Full

1.7

1.8

1.9

V

DRVDD

Full

1.7

1.8

1.9

V

SPIVDD

Full

1.7

1.8

3.6

V

Supply Current, Clock Divider = 1

Full

145

mA

Full

701

mA

Full

56

mA

Full

180

mA

Full

0.005

mA

POWER CONSUMPTION

Clock Divider = 1

Normal Operation1

Full

2160

2236

mW

Standby Power4

Full

80

mW

Power-Down Power

Full

1

mW

1

Measured with a low input frequency, full-scale sine wave.

2

Input capacitance refers to the effective capacitance between one differential input pin and AGND.

3

Input resistance refers to the effective resistance between one differential input pin and AGND.

4

Standby power is measured with a dc input and the CLK± pins inactive (that is, set to AVDD or AGND).

Rev. A | Page 3 of 36