AD9652BBCZ-310 datasheet(21/36 Pages) AD

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Data Sheet

AD9652

Rev. A | Page 21 of 36

input level at the analog inputs and adjusts the VCM output

level to keep the common-mode input voltage at an optimal

level. If both channels are operational, Channel A is monitored.

However, if Channel A is in power-down or standby mode, then

Channel B input is monitored.

Dither

The AD9652 has an optional internal dither circuitry that can be

used to improve SFDR, particularly for small signals. Dithering is

the act of injecting a known but random amount of white noise

into the input of the AD9652. Dithering has the effect of improving

the local linearity within the ADC transfer function. The AD9652

allows dither to be added to either ADC input independently.

The full scale of the dither DAC is small enough that enabling

dither does not limit the external input signal amplitude.

As shown in Figure 52, the dither that is added to the input of

the ADC through the dither DAC is precisely subtracted out

digitally to minimize SNR degradation. When dithering is

enabled, the dither DAC is driven by a pseudorandom number

generator (PN gen). In the AD9652, the dither DAC is precisely

calibrated to result in only a very small degradation in SNR and

SINAD when dither is enabled.

ADC CORE

DITHER

DAC

PN GEN

DITHER ENABLE

AD9652

VIN±x

DOUT

Figure 52. Dither Block Diagram

The SFDR improvement comes at the expense of SNR

degradation, but because the dither is internal and can be

correlated, the impact on SNR is typically limited to less than

0.5 dB in the first Nyquist zone. Enabling internal dither does

not impact full-scale dynamic range. The magnitude of dither is

controllable, which allows the user to select the desired trade-

off between SFDR improvement vs. SNR degradation.

To enable dither, set Bit 4 of Register 0x30. To modify the dither

gain, use Register 0x212[7:4].

Table 10. Dither Gain

Gain Ratio

Gain (%)

0b0000 (default)

Maximum dither

100

0b0001

255/256 × max

99.6

0b0010

254/256 × max

99.2

0b0011

252/256 × max

98.4

0b0100

248/256 × max

96.8

0b0101

240/256 × max

93.75

0b0110

224/256 × max

87.5

0b0111

192/256 × max

0b1000

Minimum dither

Large Signal Fast Fourier Transform

In most cases, dithering does not improve SFDR for large signal

inputs close to full scale, for example, with a −1 dBFS input. For

large signal inputs, the SFDR is typically limited by front-end

sampling distortion, which dithering cannot improve. However,

even for such large signal inputs, dithering may be useful for

certain applications because it makes the noise floor whiter. As

is common in pipeline ADCs, the AD9652 contains small DNL

errors caused by random component mismatches that produce

spurs or tones that make the noise floor somewhat randomly

colored device-to-device. Although these tones are typically at

very low levels and do not limit SFDR when the ADC is

quantizing large signal inputs, dithering converts these tones to

noise and produces a whiter noise floor.

Small Signal FFT

For small signal inputs, the front-end sampling circuit typically

contributes very little distortion, and the SFDR is likely to be

limited by tones caused by DNL errors due to random

component mismatches. Therefore, for small signal inputs

(typically, those below −6 dBFS), dithering can significantly

improve SFDR by converting these DNL tones to white noise.

Static Linearity

Dithering also removes sharp local discontinuities in the INL

transfer function of the ADC and reduces the overall peak-to-

peak INL.

Utilizing dither randomizes local small signal DNL errors that

produce the discontinuities in the INL transfer function and

therefore improve the peak-to-peak INL performance.

Differential Input Configurations

Optimum performance is achieved by driving the AD9652 in a

differential input configuration. For baseband applications, the

ADL5566, AD8138, ADA4937-2, ADA4938-2, and ADA4930-2

differential drivers provide excellent performance and a flexible

interface to the ADC.

The output common-mode voltage of the ADA4930-2 is easily

set with the VCM pin of the AD9652 (see Figure 53), and the

driver can be configured in a Sallen-Key filter topology to

provide band limiting of the input signal.

VIN±x

76.8Ω

120Ω

0.1µF

200Ω

90Ω

0.1µF

33Ω

15Ω

5pF

15pF

ADC

VIN–x

VIN+x

VCM

ADA4930-2

Figure 53. Differential Input Configuration Using the ADA4930-2

For baseband applications where SNR is a key parameter,

differential transformer coupling is the recommended input

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