AD9652

Data Sheet

Parameter

Test Conditions/Comments

Temperature

Min

Typ

Max

Unit

LOGIC INPUT (CSB)2

High Level Input Voltage

Full

1.22

SPIVDD

V

Low Level Input Voltage

Full

0

0.6

V

High Level Input Current

Full

−65

+65

µA

Low Level Input Current

Full

−135

0

µA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

2

pF

LOGIC INPUT (SCLK)3

High Level Input Voltage

Full

1.22

SPIVDD

V

Low Level Input Voltage

Full

0

0.6

V

High Level Input Current

Full

0

110

µA

Low Level Input Current

Full

−60

+50

µA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

2

pF

LOGIC INPUTS (SDIO)2

High Level Input Voltage

Full

1.22

SPIVDD

V

Low Level Input Voltage

Full

0

0.6

V

High Level Input Current

Full

−65

+70

µA

Low Level Input Current

Full

−135

0

µA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

5

pF

LOGIC INPUTS (PDWN)3

High Level Input Voltage

Full

1.22

DRVDD

V

Low Level Input Voltage

Full

0

0.6

V

High Level Input Current

Full

−80

+190

µA

Low Level Input Current

Full

−145

+130

µA

Input Resistance

Full

26

kΩ

Input Capacitance

Full

5

pF

DIGITAL OUTPUTS

LVDS Data and OR± Outputs

Assumes nominal 100 Ω

differential termination

ANSI Mode

Maximum setting, default

Full

310

350

450

mV

Full

1.15

1.22

1.35

V

Reduced Swing Mode

Minimum setting

Full

150

200

280

mV

Full

1.15

1.22

1.35

V

1

Input capacitance/resistance refers to the effective capacitance/resistance between one differential input pin and AGND.

2

Internal weak pull-up.

3

Internal weak pull-down.

Rev. A | Page 6 of 36