AD9652BBCZ-310 datasheet(11/36 Pages) AD

11 / 36 page

Data Sheet

AD9652

Rev. A | Page 11 of 36

Pin No.

Mnemonic

Type

Description

DRGND

Digital Ground

Digital and Output Driver Ground Reference.

DRGND

Digital Ground

Digital and Output Driver Ground Reference.

DRGND

Digital Ground

Digital and Output Driver Ground Reference.

DRGND

Digital Ground

Digital and Output Driver Ground Reference.

DRGND

Digital Ground

Digital and Output Driver Ground Reference.

DRGND

Digital Ground

Digital and Output Driver Ground Reference.

J10

DRGND

Digital Ground

Digital and Output Driver Ground Reference.

ADC Analog

VIN+A

Input

Differential Analog Input Pin (+) for Channel A.

VIN−A

Input

Differential Analog Input Pin (−) for Channel A.

VIN+B

Input

Differential Analog Input Pin (+) for Channel B.

VIN−B

Input

Differential Analog Input Pin (−) for Channel B.

VCM

Output

Common-Mode Level Bias Output for Analog Inputs. Decouple

this pin to ground using a 0.1 μF capacitor.

RBIAS

Output

External Bias Resister Connection. A 10 kΩ resister must be

connected between this pin and analog ground (AGND).

A12

VREF

Input/Output

Voltage Reference Input/Output.

A11

SENSE

Input

Reference Mode Selection (See Table 12).

CLK+

Input

ADC Clock Input (True).

CLK−

Input

ADC Clock Input (Complement).

Digital Inputs

TEST

Input

Pull-Down. Unused digital input, pull to ground through a 50 Ω

resistor.

SYNC

Input

Digital Input Clock Synchronization Pin. Tie low if unused.

PDWN

Input

Power-Down Input (Active High). The operation of this pin

depends on the SPI mode and can be configured as power-down

or standby (see Register 0x08 in Table 17).

Digital Outputs

D0+

Output

Channel A/Channel B LVDS Output Data 0 (True, LSB).

D0−

Output

Channel A/Channel B LVDS Output Data 0 (Complement, LSB).

D1+

Output

Channel A/Channel B LVDS Output Data 1 (True).

D1−

Output

Channel A/Channel B LVDS Output Data 1 (Complement).

D2+

Output

Channel A/Channel B LVDS Output Data 2 (True).

D2−

Output

Channel A/Channel B LVDS Output Data 2 (Complement).

D3+

Output

Channel A/Channel B LVDS Output Data 3 (True).

D3−

Output

Channel A/Channel B LVDS Output Data 3 (Complement).

D4+

Output

Channel A/Channel B LVDS Output Data 4 (True).

D4−

Output

Channel A/Channel B LVDS Output Data 4 (Complement).

D5+

Output

Channel A/Channel B LVDS Output Data 5 (True).

D5−

Output

Channel A/Channel B LVDS Output Data 5 (Complement).

D6+

Output

Channel A/Channel B LVDS Output Data 6 (True).

D6−

Output

Channel A/Channel B LVDS Output Data 6 (Complement).

D7+

Output

Channel A/Channel B LVDS Output Data 7 (True).

D7−

Output

Channel A/Channel B LVDS Output Data 7 (Complement).

D8+

Output

Channel A/Channel B LVDS Output Data 8 (True).

D8−

Output

Channel A/Channel B LVDS Output Data 8 (Complement).

D9+

Output

Channel A/Channel B LVDS Output Data 9 (True).

D9−

Output

Channel A/Channel B LVDS Output Data 9 (Complement).

D10+

Output

Channel A/Channel B LVDS Output Data 10 (True).

D10−

Output

Channel A/Channel B LVDS Output Data 10 (Complement).

L10

D11+

Output

Channel A/Channel B LVDS Output Data 11 (True).

M10

D11−

Output

Channel A/Channel B LVDS Output Data 11 (Complement).

L11

D12+

Output

Channel A/Channel B LVDS Output Data 12 (True).

M11

D12−

Output

Channel A/Channel B LVDS Output Data 12 (Complement).

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