AD9652BBCZ-310 datasheet(24/36 Pages) AD

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AD9652

Data Sheet

Clock Input Options

The AD9652 has a very flexible clock input structure. The clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, clock source jitter is

of the most concern, as described in the Jitter Considerations

section.

Figure 60 and Figure 61 show two preferable methods for

clocking the AD9652 (at clock rates of up to 1240 MHz). A low

jitter clock source is converted from a single-ended signal to a

differential signal using an RF balun or RF transformer.

The RF balun configuration is recommended for clock

frequencies between 125 MHz and 1240 MHz, and the RF

transformer is recommended for clock frequencies from

80 MHz to 200 MHz. The back-to-back Schottky diodes are

used across the transformer secondary or the balun balanced

side to limit clock amplitude excursions into the AD9652 to

approximately 0.8 V p-p differential. This limit helps prevent

large voltage swings of the clock from feeding through to other

portions of the AD9652, while preserving fast rise and fall times

of the clock, which are critical to low jitter performance.

390pF

SCHOTTKY

DIODES:

HSMS2822

CLOCK

INPUT

50Ω

100Ω

CLK–

CLK+

ADC

Mini-Circuits®

ADT1-1WT, 1:1Z

XFMR

Figure 60. Transformer-Coupled Differential Clock (Up to 200 MHz)

390pF

CLOCK

INPUT

1nF

25Ω

CLK–

CLK+

SCHOTTKY

DIODES:

HSMS2822

ADC

Figure 61. Balun-Coupled Differential Clock (Up to 1240 MHz)

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

pins as shown in Figure 62. The AD9510, AD9511, AD9512,

AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520,

AD9522, AD9523, AD9524, and ADCLK905/ADCLK907/

ADCLK925 clock drivers offer excellent jitter performance.

100Ω

0.1µF

240Ω

PECL DRIVER

50kΩ

CLK–

CLK+

CLOCK

INPUT

CLOCK

INPUT

AD95xx

ADC

Figure 62. Differential PECL Sample Clock (Up to 1240 MHz)

A third option is to ac couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 63. The AD9510,

AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517,

AD9518, AD9520, AD9522, AD9523, and AD9524 clock drivers

offer excellent jitter performance.

0Ω

0.1µF

50kΩ

CLK–

CLK+

CLOCK

INPUT

CLOCK

INPUT

AD95xx

LVDS DRIVER

ADC

Figure 63. Differential LVDS Sample Clock (Up to 625 MHz)

Input Clock Divider

The AD9652 contains an input clock divider with the ability to

divide the input clock by integer values of 1, 2, 4 or 8. In these

cases, the DCS is enabled by default on power-up. The clock

divide ratio is set in Register 0x0B.

The AD9652 clock divider can be synchronized using the

external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the

clock divider to be resynchronized on every SYNC signal or

only on the first SYNC signal after the register is written. A

valid SYNC causes the clock divider to reset to its initial state.

This synchronization feature allows multiple devices to have

their clock dividers aligned to guarantee simultaneous input

sampling. With the divider enabled and the SYNC option used,

the ADC clock divider output phase can be adjusted after

synchronization in increments of input clock cycles using

Drive the SYNC input using a single-ended CMOS type signal.

If not used, connect the SYNC pin to ground.

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals and, as a result, may be

sensitive to clock duty cycle. Commonly, a ±5% tolerance is

required on the clock duty cycle to maintain dynamic

performance characteristics.

The AD9652 contains a clock DCS that retimes the nonsampling

(falling) edge, providing an internal clock signal with a nominal

50% duty cycle. This allows the user to provide a wide range of

clock input duty cycles without affecting the performance of the

AD9652.

Jitter on the rising edge of the input clock is still of paramount

concern and is not reduced by the duty cycle stabilizer. The

DCS control loop does not function for clock rates less than

80 MHz nominally. The loop has a time constant associated

with it that must be considered when the clock rate changes

dynamically. A wait time of 1.5 µs to 5 µs is required after a

dynamic clock frequency increase or decrease before the DCS

loop is relocked to the input clock. During that time period, the

loop is not locked, the DCS loop is bypassed, and internal

device timing is dependent on the duty cycle of the input clock

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