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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DP83256VF 데이터시트(PDF) 30 Page - National Semiconductor (TI) |
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DP83256VF 데이터시트(HTML) 30 Page - National Semiconductor (TI) |
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30 / 144 page  30 Functional Description (Continued) INTERFACE ACTIVATION The Primary PMD Interface is always enabled The Alternate PMD Interface is enabled by programming a PLAYERa register bit To enable the interface writea1to the APMDEN bit in the APMDREG register The interface is off by default and should be left that way unless it is being used It will also probably be necessary to enable the Transmit Clocks when using the Alternate PMD Interface The Trans- mit Clocks (TXC) are enabled by writing a 1 to the TXCE bit in the CGMREG register The transmit clocks are disabled by default and should be left that way unless it is being used Note that when the Alternate PMD Interface is active the Primary PMD Interface can not be used without the Alter- nate PMD Interface connections Also note that the Long Internal Loopback (LILB) can not be used when the Alter- nate PMD Interface is activated 30 |
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