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DP83256VF 데이터시트(PDF) 96 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 DP83256VF
상세설명  PLAYERa??Device (FDDI Physical Layer Controller)
PDF  144 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83256VF 데이터시트(HTML) 96 Page - National Semiconductor (TI)

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60 Signal Descriptions (Continued)
Alternate PMD Interface
Symbol
Pin
IO
Description
PMIDa
42
I
PMD Indicate Data
Differential 100k ECL 125 Mbps serial data input signals from the PMD
Receiver into the Clock Recovery Module (CRM) of the PLAYERa
PMIDb
41
RXC
OUTa
36
O
Recovered Clock Out
125 MHz clock recovered by the Clock Recovery Module (CRM) from the
PMID data input
RXC
OUTb
35
These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD
Register (APMDREG) is set to a 1 and are off by default after Reset
When these two pins are not used they should be left Not Connected (NC)
RXD
OUTa
52
O
Recovered Data Out
125 Mbps data recovered by the Clock Recovery Module (CRM) from the
PMID data input
RXD
OUTb
51
These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD
Register (APMDREG) is set to a 1 and are off by default after Reset
When these two pins are not used they should be left Not Connected (NC)
RXC
INa
48
I
Receive Clock In
Clock inputs to the Player section of the PLAYERa These inputs must be
synchronized with the RXD
IN inputs
RXC
INb
47
These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD
Register (APMDREG) is set to a 1 and are off by default after Reset
When these two pins are not used pin 76 should be left Not Connected (NC) and pin 75 should be
connected directly to ground (Reserved
0)
RXD
INa
50
I
Receive Data In
Data inputs to the Player section of the PLAYERa These inputs must be
synchronized with the RXC
IN inputs
RXD
INb
49
These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD
Register (APMDREG) is set to a 1 and are off by default after Reset
When these two pins are not used pin 78 should be left Not Connected (NC) and pin 77 should be
connected directly to ground (Reserved
0)
PMRDa
34
O
PMD Request Data
Differential 100k ECL 125 Mbps serial data output signals to the PMD
transmitter
PMRDb
33
TXCa
31
O
Transmit Clock
125 MHz 100k ECL compatible differential outputs synchronized to the outgoing
PMRD data
TXCb
30
These signals can be enabled using the Transmit Clock Enable (TXCE) bit in the Clock Generation
Module Register (CGMREG)
When these two pins are not used they should be left Not Connected (NC)
SDa
40
I
Signal Detect
Differential 100k ECL input signals from the PMD receiver indicating that a signal
is being received by the PMD receiver
SDb
39
96



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