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DP83256VF 데이터시트(PDF) 100 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 DP83256VF
상세설명  PLAYERa??Device (FDDI Physical Layer Controller)
PDF  144 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83256VF 데이터시트(HTML) 100 Page - National Semiconductor (TI)

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60 Signal Descriptions (Continued)
MISCELLANEOUS INTERFACE
The Miscellaneous Interface consist of a reset signal and user definable enable signals
Symbol
Pin
IO
Description
E
RST
71
I
Reset
An active low TTL input signal which clears all registers The signal must be kept asserted for a
minimum amount of time Once the ERST signal is asserted the PLAYERa device should be allowed
the specified amount of time to reset internal logic Note that bit zero of the Mode Register will be set to
zero (ie Stop Mode) See section 42 Stop Mode of Operation for more information
EP0
41
O
User Definable Enable Pin 0
A TTL output signal allowing control of external logic through the Control
Bus Interface EP0 is asserteddeasserted through Enable Bit 0 (EB0) of the User Definable Register
(UDR) When Enable Bit 0 is set to zero EP0 is deasserted When Enable Bit 0 is set to one EP0 is
asserted
EP1
43
O
User Definable Enable Pin 1
A TTL output signal allowing control of external logic through the Control
Bus Interface EP1 is asserteddeasserted through Enable Bit 1 (EB1) of the User Definable Register
(UDR) When Enable Bit 1 is set to zero EP1 is deasserted When Enable Bit 1 is set to one EP1 is
asserted
100



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