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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DP83256VF 데이터시트(PDF) 56 Page - National Semiconductor (TI) |
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DP83256VF 데이터시트(HTML) 56 Page - National Semiconductor (TI) |
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56 / 144 page  50 Registers (Continued) 512 RECEIVE CONDITION MASK REGISTER A (RCMRA) The Receive Condition Mask Register A allows the user to dynamically select which events will generate an interrupt The Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the Receive Condition Register A (RCRA) is set to 1 and the corresponding mask bit(s) in this register is also set to 1 Since this register is cleared (ie set to 0) during the reset process all interrupts are initially masked ACCESS RULES ADDRESS READ WRITE 0Bh Always Always D7 D6 D5 D4 D3 D2 D1 D0 LSUPIM LSCM NTM NLSM MLSM HLSM QLSM NSDM Bit Symbol Description D0 NSDM NO SIGNAL DETECT MASK The mask bit for the No Signal Detect bit (NSD) of the Receive Condition Register A (RCRA) D1 QLSM QUIET LINE STATE MASK The mask bit for the Quiet Line State bit (QLS) of the Receive Condition Register A (RCRA) D2 HLSM HALT LINE STATE MASK The mask bit for the Halt Line State bit (HLS) of the Receive Condition Register A (RCRA) D3 MLSM MASTER LINE STATE MASK The mask bit for the Master Line State bit (MLS) of the Receive Condition Register A (RCRA) D4 NLSM NOISE LINE STATE MASK The mask bit for the Noise Line State bit (NLS) of the Receive Condition Register A (RCRA) D5 NTM NOISE THRESHOLD MASK The mask bit for the Noise Threshold bit (NT) of the Receive Condition Register A (RCRA) D6 LSCM LINE STATE CHANGE MASK The mask bit for the Line State Change bit (LSC) of the Receive Condition Register A (RCRA) D7 LSUPIM LINE STATE UNKNOWN AND PHY INVALID MASK The mask bit for the Line State Unknown and PHY Invalid bit (LSUPI) of the Receive Condition Register A (RCRA) 56 |
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