DP83256VF datasheet(102/144 Pages) NSC

102 / 144 page

60 Signal Descriptions (Continued)

63 DP83257VF SIGNAL DESCRIPTIONS

The pin descriptions for the DP83257VF are divided into five functional interfaces PMD Interface PHY Port Interface Control

Bus Interface Clock Interface and Miscellaneous Interface

For a Pinout Summary List refer to Table 8-3 and

Figure 8-3 DP83257VF 160-Pin JEDEC Metric PQFP Pinout

PMD INTERFACE

The PMD Interface consists of IO signals used to connect the PLAYERa device to the Physical Medium Dependant (PMD)

sublayer

The DP83257 PLAYERa device actually has two PMD interfaces The Primary PMD Interface and the Alternate PMD Interface

The Primary PMD Interface should be used for all PMD implementations that do not require an external scramblerdescrambler

function clock recovery function or clock generation function such as a Fiber Optic or Shielded Twisted Pair (SDDI) PMD The

second Alternate PMD Interface can be used to support Unshielded Twisted Pair (UTP) PMDs that require external scrambling

with no external clock recovery or clock generation functions required

Section 38 describes how the PLAYERa can be connected to the PMD and how the Alternate PMD can be enabled

Note that when the Alternate PMD Interface is not being used the pins that make up the interface must be connected in the

specific way described in the following Alternate PMD Interface table

Primary PMD Interface

Symbol

Description

PMIDa

PMD Indicate Data

Differential 100k ECL 125 Mbps serial data input signals from the PMD Receiver

into the Clock Recovery Module (CRM) of the PLAYERa

PMIDb

PMRDa

PMD Request Data

Differential 100k ECL 125 Mbps serial data output signals to the PMD transmitter

PMRDb

SDa

Signal Detect

Differential 100k ECL input signals from the PMD receiver indicating that a signal is being

received by the PMD receiver

SDb

TEL

PMD Transmitter Enable Level

A TTL input signal to select the PMD transmitter Enable (TXE) signal

level

TXE

PMD Transmitter Enable

A TTL output signal to enabledisable the PMD transmitter The output level

of the TXE pin is determined by three parameters the Transmit Enable (TE) bit in the Mode Register the

TM2 – TM0 bits in the Current Transmit State Register and the input to the TEL pin The following rules

summarize the output of the TXE pin

1 If TEe0 and TELeGND then TXEeVCC

2 If TEe0 and TELeVCC then TXEeGND

3 If TEe1 and OTM and TELeGND then TXEeVCC

4 If TEe1 and OTM and TELeVCC then TXEeGND

5 If TEe1 and not OTM and TELeGND then TXEeGND

6 If TEe1 and not OTM and TELeVCC then TXEeVCC

102

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