DP83901AV datasheet(3/62 Pages) NSC

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Pin Description

Pin No

Pin Name

Description

BUS INTERFACE PINS

PRD

PORT READ

Enables data from external latch on to local bus during a memory write cycle to

local memory (remote write operation) This allows asynchronous transfer of data from the

system memory to local memory

3 – 6

RA0 – RA3

These four pins are used to select a register to be read or written The

state of these inputs is ignored when the NIC is not in slave mode (CS high)

7 – 17

AD0 – AD15

IO Z

MULTIPLEXED ADDRESSDATA BUS

22 – 25

used to read and write register data AD8–AD15 float during IO transfers SRD SWR pins are

used to select direction of transfer

Bus Master with BACK input asserted

During t1 of memory cycle AD0 – AD15 contain address

During t2 t3 t4 AD0 – AD15 contain data (word transfer mode)

During t2 t3 t4 AD0 – AD7 contain data AD8 – AD15 contain address (byte transfer mode)

Direction of transfer is indicated by SNIC on MWR MRD lines

ADS0

IO Z

ADDRESS STROBE 0

Input with DMA inactive and CS low latches RA0–RA3 inputs on falling edge If high data

present on RA0–RA3 will flow through latch

Output When Bus Master latches address bits (A0–A15) to external memory during DMA

transfers

CHIP SELECT

Chip Select places controller in slave mode for mP access to internal registers

Must be valid through data portion of bus cycle RA0 – RA3 are used to select the internal

MWR

O Z

MASTER WRITE STROBE

(Strobe for DMA transfers)

Active low during write cycles (t2 t3 tw) to buffer memory Rising edge coincides with the

presence of valid output data TRI-STATE until BACK asserted

MRD

O Z

MASTER READ STROBE

(Strobe for DMA transfers)

Active during read cycles (t2 t3 tw) to buffer memory Input data must be valid on rising edge of

MRD TRI-STATE until BACK asserted

SWR

SLAVE WRITE STROBE

Strobe from CPU to write an internal register selected by RA0 – RA3

Data is latched into the SNIC on the rising edge of this input

SRD

SLAVE READ STROBE

Strobe from CPU to read an internal register selected by RA0 – RA3

The register data is output when SRD goes low

ACK

ACKNOWLEDGE

Active low when SNIC grants access to CPU Used to insert WAIT states to

CPU until SNIC is synchronized for a register read or write operation

BSCK

BUS CLOCK

This clock is used to establish the period of the DMA memory cycle Four clock

cycles (t1 t2 t3 t4) are used per DMA cycle DMA transfers can be extended by one BSCK

increments using the READY input

RACK

READ ACKNOWLEDGE

Indicates that the system DMA or host CPU has read the data placed

in the external latch by the SNIC The SNIC will begin a read cycle to update the latch

PWR

PORT WRITE

Strobe used to latch data from the SNIC into external latch for transfer to host

memory during Remote Read transfers The rising edge of PWR coincides with the presence of

valid data on the local bus

READY

This pin is set high to insert wait states during a DMA transfer The SNIC will sample this

signal at t3 during DMA transfers

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