DP83901AV datasheet(40/62 Pages) NSC

40 / 62 page

130 Bus Arbitration and Timing (Continued)

FIFO AT THE BEGINNING OF RECEIVE

At the beginning of reception the SNIC stores entire Ad-

dress field of each incoming packet in the FIFO to deter-

mine whether the packet matches its Physical Address Reg-

ister or maps to one of its Multicast Registers This causes

the FIFO to accumulate 8 bytes Furthermore there are

some synchronization delays in the DMA PLA Thus the

actual time that BREQ is asserted from the time the Start of

Frame Delimiter (SFD) is detected is 78 ms This operation

affects the bus latencies at 2 byte and 4 byte thresholds

during the first receive BREQ since the FIFO must be filled

to 8 bytes (or 4 words) before issuing a BREQ

FIFO Operation at the End of Receive

When Carrier Sense goes low the SNIC enters its end of

packet processing sequence emptying its FIFO and writing

the status information at the beginning of the packet

Figure

5 The SNIC holds onto the bus for the entire sequence The

longest time BREQ may be extended occurs when a packet

ends just as the SNIC performs its last FIFO burst The

SNIC in this case performs a programmed burst transfer

followed by flushing the remaining bytes in the FIFO and

completes by writing the header information to memory The

following steps occur during this sequence

1 SNIC issues BREQ because the FIFO threshold has been

reached

2 During the burst packet ends resulting in BREQ extend-

3 SNIC flushes remaining bytes from FIFO

4 SNIC performs internal processing to prepare for writing

the header

5 SNIC writes 4-byte (2-word) header

6 SNIC deasserts BREQ

End of Packet Processing

TLF10469 – 53

End of Packet Processing (EOPP) times for 10 MHz and

20 MHz have been tabulated below

End of Packet Processing Times for Various FIFO

Thresholds Bus Clocks and Transfer Modes

Mode

Threshold

Bus Clock

EOPP

Byte

2 bytes

70 ms

4 bytes

10 MHz

86 ms

8 bytes

110 ms

Byte

2 bytes

36 ms

4 bytes

20 MHz

42 ms

8 bytes

50 ms

Word

2 bytes

54 ms

4 bytes

10 MHz

62 ms

8 bytes

74 ms

Word

2 bytes

30 ms

4 bytes

20 MHz

32 ms

8 bytes

36 ms

Maximum Bus Latency for Byte Mode

TLF10469 – 54

Maximum Bus Latency for Word Mode

TLF10469 – 55

DP83901AV 데이터시트(PDF) 40 Page - National Semiconductor (TI)

DP83901AV 데이터시트(HTML) 40 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

데이터시트 다운로드

링크 URL