DP83901AV datasheet(4/62 Pages) NSC

4 / 62 page

Pin Description (Continued)

Pin No

Pin Name

Description

BUS INTERFACE PINS

(Continued)

PRQADS1

O Z

PORT REQUESTADDRESS STROBE 1

32-BIT MODE If LAS is set in the Data Configuration Register this line is programmed

as ADS1 It is used to strobe addresses A16 – A31 into external latches (A16 – A31 are the

fixed addresses stored in RSAR0 RSAR1) ADS1 will remain at TRI-STATE until BACK is

received

16-BIT MODE If LAS is not set in the Data Configuration Register this line is programmed as

PRQ and is used for Remote DMA Transfers The SNIC initiates a single remote DMA read or

write operation by asserting this pin In this mode PRQ will be a standard logic output

Note

This line will power up as TRI-STATE until the Data Configuration Register is programmed

BACK

BUS ACKNOWLEDGE

Bus Acknowledge is an active high signal indicating that the CPU has

granted the bus to the SNIC If immediate bus access is desired BREQ should be tied to BACK

Tying BACK to VCC will result in a deadlock

BREQ

BUS REQUEST

Bus Request is an active high signal used to request the bus for DMA transfers

This signal is automatically generated when the FIFO needs servicing

RESET

Reset is active low and places the SNIC in a reset immediately no packets are

transmitted or received by the SNIC until STA bit is set Affects Command Register Interrupt

Mask Register Data Configuration Register and Transmit Configuration Register The SNIC will

execute reset within 10 BSCK cycles and TXC cycles

INT

INTERRUPT

Indicates that the SNIC requires CPU attention after reception transmission or

completion of DMA transfers The interrupt is cleared by writing to the ISR (Interrupt Service

WACK

WRITE ACKNOWLEDGE

Issued from system to SNIC to indicate that data has been written to

the external latch The SNIC will begin a write cycle to place the data in local memory

NETWORK INTERFACE PINS

TXb

TRANSMIT OUTPUT

Differential driver which sends the encoded data to the transceiver The

outputs are source followers which require 270X pulldown resistors

TXa

TEST

FACTORY TEST INPUT

Used to check the chip’s internal functions Tied low during normal

operation

SEL

MODE SELECT

When high Transmita and Transmitb are the same voltage in the idle state

When low Transmita is positive with respect to Transmitb in the idle state at the transformer’s

primary

EXTERNAL OSCILLATOR INPUT

GNDX2

GROUNDX2

This in should normally be connected to ground It is possible to use a crystal

oscillator using X1 and GNDX2 if certain precautions are taken Contact National

Semiconductor for more information

SNISEL

FACTORY TEST INPUT

For normal operation tied to VCC When low enables the ENDEC

module to be tested independently of the SNIC module

RXb

RECEIVE INPUT

Differential receive input pair from the transceiver

RXa

CDb

COLLISION INPUT

Differential collision pair input from the transceiver

CDa

DP83901AV 데이터시트(PDF) 4 Page - National Semiconductor (TI)

DP83901AV 데이터시트(HTML) 4 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

데이터시트 다운로드

링크 URL