DP83907 datasheet(48/70 Pages) NSC

48 / 70 page

60 Operation of DP83907 (Continued)

65 LOOPBACK DIAGNOSTICS

Three forms of local Ioopback are provided on the

DP83907 The user has the ability to loopback through the

deserializer on the controller through the ENDEC module or

transceiver Because of the half duplex architecture of

the DP83907 loopback testing Is a special mode of op-

eration with the following restrictions

Restrictions During Loopback

The FlFO is split into two halves one half is used for trans-

mission the other for reception Only 8-bit fields can be

fetched from memory so two tests are required for 16-bit

systems to verify integrity of the entire data path During

loopback the maximum latency to obtain access to the buff-

er memory is 20 ms Systems that wish to use the loopback

test yet do not meet this latency can limit the loopback

packet to 7 bytes without experiencing underflow Only the

last 8 bytes of the loopback packet are retained in the FlFO

The last 8 bytes can be read through the FIFO register

which will advance through the FIFO to allow reading the

receive packet sequentially

Destination Address

6 bytes Station Physical

Address

Source Address

6 bytes Station Physical

Address

Length

2 bytes

Data

46 to 1500 bytes

CRC

Appended by DP8307

Controller if CRC e 0inTCR

When in word-wide mode with Byte Order Select set the

loopback packet must be assembled in the even byte loca-

tions as shown below (The loopback only operated with

byte wide transfers)

LS Byte (D8–D15)

MS Byte (D0–D7)

Destination

Source

Length

Data

CRS

WTS e 1

BOS e 1

(DCR Bits)

When in word-wide mode with Byte Order Select low the

following format must be used for the loopback packet

MS Byte (D8–D15)

LS Byte (D0–D7)

Destination

Source

Length

Data

CRS

WTS e1

BOS e 0

(DCR Bits)

Note

When using loopback in word mode 2n bytes must be programmed in

the TBCR0 1 When n e actual number of bytes assembled in even

or odd location

To initiate a loopback the user first assembles the loopback

packet then selects the type of loopback using the Transmit

Configuration register bits LB0 LB1 The transmit configura-

tion register must also be set to enable or disable CRC gen-

eration during transmission The user then issues a normal

transmit command to send the packet During loopback the

receiver checks for an address match and if CRC bit in the

TCR is set the receiver will also check the CRC The last 8

bytes of the loopback packet are buffered and can read out

of the FlFO using FlFO read port

Loopback Modes

MODE1

Loopback Through the DP83907 Controller Mod-

ule (LB1 e 0 LB0 e 1) If this loopback is used The

DP83907 Module’s serializer is connected to the deserializ-

MODE 2

Loopback Through the ENDEC Module (LB1 e 1

LB0 e 0) If the loopback is to be performed through the

SNI the DP83907 provides a control (LPBK) that forces the

ENDEC module to loopback all signals

MODE 3

Loopback to the external coax interface or twisted

pair interface module (LB1 e 1 LB0 e 1)

Packets can be transmitted to the cable in loopback mode

to check all of the transmit and receive paths and the cable

itself If in twisted pair mode there is a link fail the transmit-

ter will be disabled which could give misleading results in

Mode 3 The link integrity should be checked by reading

Configuration Register B before this test

Reading the Loopback Packet

The last eight bytes of a received packet can be examined

by 8 consecutive reads of the FlFO register The FIFO point-

er is increment after the rising edge of the CPU’s read

strobe by internally synchronizing and advancing the point-

er This may take up to four bus clock cycles if the pointer

has not been incremented by the time the CPU reads the

FIFO register again the DP83907 will insert wait states

Note

The FIFO may only be read during Loopback Reading the FIFO at

any other time will cause the DP83907 to malfunction

Alignment of the Received Packet In the FIFO

Reception of the packet in the FIFO begins at location zero

after the FIFO pointer reaches the last location in the FlFO

the pointer wraps to the top of the FlFO overwriting the

previously received data This process continued until the

last byte is received The DP83907 then appends the re-

ceived byte count in the next two locations of the FIFO The

contents of the Upper Byte Count are also copied to the

next FlFO location The number of bytes used in the loop-

back packet determined the alignment of the packet in the

FlFO The alignment for a 64-byte packet is shown below

FIFO

FIFO Contents

Location

Lower Byte Count

First Byte Read

Upper Byte Count

Second Byte Read

Upper Byte Count

Last Byte

CRC1

CRC2

CRC3

CRC4

Last Byte Read

DP83907 데이터시트(PDF) 48 Page - National Semiconductor (TI)

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