DP83907 datasheet(59/70 Pages) NSC

59 / 70 page

70 In-Circuit Test (ICT) Description

The test register is made available only when the test bit (D7 of cnfg A) is set at the following IO address

IO mode Base a 1FHex

The test register contains the following bits Note that when the test bit is low the test register is held set except for D4 and D0

which is reset

TABLE I Test Modes (test pin e 1)

Test Mode

SAk9l

1VIH VIL

11111110

2VOH VOL

11101010

VIL VIH test mode when high will AND all inputs (except RESET pin) and present outcome on IRQk3l To enable this st-nic

mode must NOT be entered

VOH VOL test mode is active in st-nic mode if SAk9le1 Then all op’s switch with SAk4l as per Table 2

VOH VOL mode output states (SAk9le1)

TABLE II

Output

SAk4le0SAk4le1

MSAk131l

1555 Hex

0AAA Hex

MSDk150l

AAAA Hex

5555 Hex

SDk150l

AAAA Hex

5555 Hex

IRQk15 12 11 10 9 5 4 3l

A2 Hex

5D Hex

MSWR

MSRD

RCS

BPCS

EECS

IO16

CHRDY (AEN AORD Must be Low)

GDLNK ACT COL

0 1 0

1 0 1

THIN

DP83907 데이터시트(PDF) 59 Page - National Semiconductor (TI)

DP83907 데이터시트(HTML) 59 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

데이터시트 다운로드

링크 URL