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DP83907 데이터시트(PDF) 17 Page - National Semiconductor (TI) |
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DP83907 데이터시트(HTML) 17 Page - National Semiconductor (TI) |
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17 / 70 page ![]() 40 Functional Description (Continued) Receiver and Smart Squelch The DP83907 implements an intelligent receive squelch on the RXIg differential inputs to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal The squelch circuitry employs a combination of amplitude and timing measurements to determine the validity of data on the twisted pair inputs There are two voltage level op- tions for the smart squelch One mode 10BASE-T mode uses levels that meet the 10BASE-T specification The sec- ond mode reduced squelch mode uses a lower squelch threshold level and can be used in longer cable applica- tions where due to attenuation smaller signal levels may be present The squelch level mode can be selected in the DP83907 configuration registers Figure 14 shows the operation of the smart squelch in 10BASE-T mode The signal at the start of packet is checked by the smart squelch and any pulses not exceeding the squelch level (either positive or negative depending upon polarity) will be rejected Once this first squelch level is overcome correctly the opposite squelch level must then be exceeded within 150 ns later Finally the signal must exceed the original squelch level within a further 150 ns to ensure that the input waveform will not be rejected The checking procedure re- sults in the loss of typically three bits at the beginning of each packet Only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present At this time the smart squelch circuitry is reset In the reduced squelch mode the operation is identical ex- cept that the lower squelch levels shown in the figure are used Valid data is considered to be present until either squelch level has not been generated for a time longer than 150 ns indicating End of Packet Once good data has been detect- ed the squelch levels are reduced to minimize the effect of noise causing premature End of Packet detection Collision A collision is detected by the TPI module when the receive and transmit channels are active simultaneously If the TPI is receiving when a collision is detected it is reported to the controller immediately If however the TPI is transmitting when a collision is detected the collision is not reported until seven bits have been received while in the collision state This prevents a collision being reported incorrectly due to noise on the network The signal to the controller remains for the duration of the collision Approximately 1 msec after the transmission of each packet a signal called the Signal Quality Error (SQE) consisting of typically 10 cycles of 10 MHz is generated This 10 MHz signal also called the Heartbeat ensures the continued functioning of the collision circuitry Link DetectorGenerator The link generator is a timer circuit that generates a link pulse as defined by the 10 Base-T specification that will be generated by the transmitter section The pulse which is 100 ns wide is transmitted on the TXOa output every 16 ms in the absence of transmit data The pulse is used to check the integrity of the connection to the remote MAU The link detection circuit checks for valid pulses from the remote MAU and if valid link pulses are not received the link detector will disable the transmit receive and collision detection functions The GDLNK output can directly drive a LED to show that there is a good twisted pair link For normal conditions the LED will be on The link integrity function can be disabled by setting the GDLNK bit of Configuration Register B Jabber The jabber timer monitors the transmitter and disables the transmission if the transmitter is active for greater than 26 ms The transmitter is then disabled for the whole time that the Endec module’s internal transmit enable is asserted This signal has to be deasserted for approximately 750 ms (the unjab time) before the Jabber re-enables the transmit outputs TLF12082 – 9 FIGURE 14 Twisted Pair Squelch Waveform 17 |
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