CP3SP33SMSSLASHNOPB datasheet(38/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

Table 9-5. DSP and ASC Registers (continued)

NAME

ADDRESS

DESCRIPTION

ASCDDMASEL0

FF 6808h

ASC DSP DMA Channel Select Register 0

ASCDDMASEL1

FF 680Ch

ASC DSP DMA Channel Select Register 1

ASCDDMASEL2

FF 6810h

ASC DSP DMA Channel Select Register 2

ASCDDMASEL3

FF 6814h

ASC DSP DMA Channel Select Register 3

ASCINTSEL

FF 6818h

ASC Interrupt Controller Select Register

9.3.1

ASC DSP Control Register (ADMAC)

The ADMAC register is a 16-bit, read/write register used by the CPU to reset the DSP. After reset, this

Reserved

DSPRSTN

DSPRSTN The DSP Reset bit is used to assert reset to the DSP. The DSP reset signal is the OR

function of this bit and the CPU reset signal. CPU software must set this bit to enable the

DSP.

0 – DSP module reset.

1 – DSP module may run (if PCFG.DSPR is clear).

9.3.2

ASC DSP Status Register (ADMAS)

The ADMAS register is a 16-bit, read-only register that indicates whether the CPU host interface to the

DSP DMA controller is busy and whether the DSP in reset. After reset, this register is 0000h.

Reserved

RRSTN

PBUSY

The Port Busy bit indicates whether the CPU host interface to the DSP DMA controller is

busy. If the DSP write FIFO is full, the DSP read FIFO is empty (and a read has been

requested), or the PADR register has been written, this bit will be set. Software must poll the

PBUSY bit before using the CPU host interface to access the DSP memory space.

0 – CPU host interface is ready.

1 – CPU host interface is busy.

RRSTN

The Reflected Reset bit indicates whether the DSP is being held in reset.

0 – DSP is in reset.

1 – DSP is not in reset.

9.3.3

DSP DMA Channel 0 Data Register (PDATA)

The PDATA register is a 16-bit, read/write register that provides the CPU with access to the read and

write FIFOs for DSP DMA channel 0. Writing the register loads the write FIFO, and reading the register

unloads the read FIFO.

PDATA

DSP and Audio Peripherals

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