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CP3SP33SMS/NOPB 데이터시트(PDF) 83 Page - Texas Instruments |
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CP3SP33SMS/NOPB 데이터시트(HTML) 83 Page - Texas Instruments |
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83 / 407 page ![]() OUT IN NMOD NDIV 32 F F MDIV PDIV § · ¨ ¸ u ¨ ¸ u ¨ ¸ ¨ ¸ © ¹ VCO IN NMOD F F 32 MDIV § · u ¨ ¸ u © ¹ (2 )/( ) 0 2 ( )cos 2 S ' ' S S ³ t n D s t nw c H w dw w CP3SP33 www.ti.com SNOSCW5 – MAY 2013 The reference frequency FREF is derived from the input frequency FIN, as described by the following equation: (1) The voltage-controlled oscillator output frequency FVCO is derived from the input frequency FIN, as described by the following equation: (2) FREF must be between 2 and 4 MHz. FVCO must not exceed 153 MHz. The output frequency FOUT is derived from the input frequency FIN, as described by the following equation: (3) It is possible for software to load divisors that result in unstable or marginally stable PLL operation. Therefore, only divisors recommended in Table 14-3 and Table 14-4 should be used. If any other frequencies are desired, contact Texas Instruments. Table 14-3. Recommended HCLK Clock Divisors FIN FOUT M Div. N Div. N Mod. P Div. (MHz) (MHz) 12 4 32 0 4 24 12 6 64 0 4 32 12 4 48 0 4 36 12 4 32 0 2 48 12 3 30 0 2 60 12 6 64 0 2 64 12 4 48 0 2 72 12 4 30 0 1 90 12 3 24 0 1 96 The PLLs are designed to drive the telematics codec and other devices with audio sample rates (Fs) of 44.1 kHz and 48 kHz (as well as 32 kHz, 24 kHz, 22.05 kHz, etc.) and 125× or 250× oversampling. Therefore, the two common clock requirements are 11.025 MHz (44.1 kHz × 250) and 12.000 MHz (48 kHz × 250). These frequencies can be obtained from any common input clock rate between 10 MHz and 20 MHz as shown in Table 14-4. Table 14-4. Recommended Audio Clock Divisors FS FIN SOURCE M Div. N Div. N Mod. P Div. (kHz) (MHz) System 44.1 11 5 55 4 11 System 44.1 11.2896 4 46 2 12 System 44.1 12 5 55 3 12 System 44.1 13 5 55 4 13 System 44.1 14.4 4 30 20 10 Copyright © 2013, Texas Instruments Incorporated Clock Generation 83 Submit Documentation Feedback Product Folder Links :CP3SP33 |
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