CP3SP33SMSSLASHNOPB datasheet(85/407 Pages) TI1

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MAIN

DESIRED

2 F

PMMAUXnPRSC

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

A 12-bit prescaler provides a prescale factors from 1 to 2048 clock periods of the input clock in increments

of 1/2 clock period. For example, if the selected clock source is 12 MHz and the desired auxiliary clock

frequency is 1 MHz, the divisor should be 2 × 12 or 24. However, the value loaded in the

PMMAUXnPRSC prescaler register is biased by 1, so the actual value loaded into the register will be 23

(decimal).

(4)

Zero is an undefined value, so the shortest period that an auxiliary clock may have is 2 half-clocks, which

results in the same clock rate as the prescaler input clock.

By default, the auxiliary clocks are disabled following reset, except the DSP clock (Auxiliary Clock 7).

Each auxiliary clock is available for one or more peripherals, as listed in Table 14-5.

Table 14-5. Auxiliary Clocks Available to Peripherals

AUXILIARY

PERIPHERAL

COMMENTS

CLOCK

Bluetooth, ADC, AAI

Bluetooth LLC requires an accurate 12 MHz clock, in addition to a variable Auxiliary Clock 1.

CVSD/PCM Converter 0

Supports a 2-MHz mode in which data is processed at a fixed rate. Also supports a free-

running mode in which data is processed on demand.

The free-running mode does not require a specific clock frequency. The CVSD modules may

CVSD/PCM Converter 1

operate from independent clocks.

Telematics Codec ADC 1,

Requires an accurate clock frequency, typically 125× or 128× the PCM frame rate.

ADC 2, and Stereo DACs

I2S Interface

USB

Requires an accurate 60 MHz clock. Also requires a HCLK Clock >30 MHz.

DSP

Up to 96 MHz

Requires an accurate frequency to match the bit clock and frame sync required by the external

AAI

codec.

Clock Generation

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