CP3SP33SMSSLASHNOPB datasheet(78/407 Pages) TI1

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Low-Frequenc y

Os c illator

X 2CK I

X 2CKO

DS431

High-Frequenc y

Os c illator

X 1CK I

X 1CKO

CLK IN

I2S CLK

System Clock

12-Bit Prescaler

Main Clock

P LL2

P MMP LL2CTL1.P LLIP S E L

P LL1

P MMP LL1CTL1.P LLIP S E L

Peripheral Bus Clock

2-Bit Prescaler

Slow Clock

14-Bit Prescaler

P MMCK CTL.FCLK S RC

P MMP RS HC.HP HCLK

P MMP RS P C.DIV P CLK

P MMP RS S C.HP S CLK

P MMCK CTL.S CLK

PLL1 Clock

PLL2 Clock

HCLK Clock

PCLK Clock

Slow Clock

Power S av e Mode

CP3SP33

SNOSCW5 – MAY 2013

www.ti.com

•

Slow Clock—32.768 kHz clock used in low-power modes. Slow Clock is generated by an on-chip

oscillator, received from an external clock source or generated by a prescaler from Main Clock.

Available prescale factors are 1 to 8192 in increments of 1/2 clock period.

Figure 14-1 is block diagram of the global clock generation logic.

Figure 14-1. Global Clock Generation

14.1 Extrnal Crystal Networks

An external crystal network is connected to the X1CKI and X1CKO pins to generate the Main Clock,

unless an external clock signal is driven on the CLKIN pin. A similar external crystal network may be used

at pins X2CKI and X2CKO for the Slow Clock. If an external crystal network is not used for the Slow

Clock, the Slow Clock is generated through a prescaler from Main Clock.

The crystal network you choose may require external components different from the ones specified in this

datasheet. In this case, consult with National’s engineers for the component specifications

The crystals and other oscillator components must be placed close to the X1CKI/X1CKO and

X2CKI/X2CKO device input pins to keep the trace lengths to an absolute minimum.

Clock Generation

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