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CP3SP33SMS/NOPB 데이터시트(PDF) 56 Page - Texas Instruments |
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CP3SP33SMS/NOPB 데이터시트(HTML) 56 Page - Texas Instruments |
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56 / 407 page ![]() CP3SP33 SNOSCW5 – MAY 2013 www.ti.com All DMA transfers are indirect mode, in which the data is read from the source into a DMAC buffer register, then written from the buffer register to the destination. Each DMAC channel has ten 32-bit control and status reg-isters. DMAC registers are named with the suffix n, in which n is 0 to 15, representing the channel number. If all of the channels are disabled (DMACNTn.CHEN = 0), the clock to the DMA module is disabled to reduce power consumption. 12.1 DMA-Capable Peripherals Table 12-1 shows the DMA-capable peripherals, which may be assigned to any of the 16 DMA channels by programming the SRCRQ field of the DMACNTn registers. The SRCRQ field only selects the source of the DMA request signal and the receiver for the DMA acknowledge signal. It is still necessary to set up the address of the peripheral, the transfer direction, and other DMA channel control settings. Table 12-1. DMA-Capable Peripherals SRCRQ PERIPHERAL TRANSACTION REGISTER ASC CHANNEL 0 UART3 R RXBUF3 0 1 UART3 W TXBUF3 1 2 CVSD/PCM0 R PCMOUT0 2 3 CVSD/PCM0 W PCMIN0 3 4 CVSD/PCM1 R PCMOUT1 4 5 CVSD/PCM1 W PCMIN1 5 6 AAI Slot 0 R ARDR0 6 7 AAI Slot 0 W ATDR0 7 8 AAI Slot 1 R ARDR1 8 9 AAI Slot 1 W ATDR1 9 10 Codec ADC1 R TCDCADC1 10 11 Codec ADC2 R TCDCADC2 11 12 Codec DAC Left W TCDCLEFT 12 13 Codec DAC Right W TCDCRIGHT 13 14 I2S Left R I2SRXDATL 14 15 I2S Right R I2SRXDATR 15 16 I2S Left W I2STXDATL 16 17 I2S Right W I2STXDATR 17 18 MWSPI1 R MWDAT 18 19 MWSPI1 W MWDAT 19 20 ACCESS.bus 1 R/W ACBSDA 20 21 USART0 R RXBUF0 22 USART0 W TXBUF0 23 UART1 R RXBUF1 24 UART1 W TXBUF1 25 UART2 R RXBUF2 26 UART2 W TXBUF2 27 CVSD/PCM0 R CVSDOUT0 28 CVSD/PCM0 W CVSDIN0 29 CVSD/PCM1 R CVSDOUT1 30 CVSD/PCM1 W CVSDIN1 31 AAI Slot 2 R ARDR2 32 AAI Slot 2 W ATDR2 56 CPU DMA Controller Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :CP3SP33 |
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