TMS320DM355CZCEA13 datasheet(86/163 Pages) TI1

86 / 163 page

TMS320DM355

SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010

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3.11.2 PLL Configuration

After POR, warm reset, and max reset, the PLLs and clocks are set to their default configurations. The

PLLs are in bypass mode and disabled by default. This means that the input reference clock at MXI1

(typically 24 MHz) drives the chip after reset. For more information on device clocking, see Section 3.5

and Section 3.6. The default state of the PLLs is reflected in the default state of the register bits in the

PLLC registers. Refer to TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem

Reference Guide (literature number SPRUFB3) for PLLC register descriptions.

3.11.3 Power Domain and Module State Configuration

Only a subset of modules are enabled after reset by default. Table 3-22 shows which modules are

enabled after reset. Table 3-22 as shows that the following modules are enabled depending on the

sampled state of the device configuration pins: EDMA (CC, TC0 and TC1), AEMIF, MMC/SD0, UART0,

and Timer0. For example, UART0 is enabled after reset when the device configuration pins (BTSEL[1:0] =

11 - Enable UART) select UART boot mode. For more information on module configuration refer to

TMS320DM35x Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature

number SPRUFB3).

Detailed Device Description

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