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TMS320DM355CZCEA13 데이터시트(PDF) 92 Page - Texas Instruments

부품명 TMS320DM355CZCEA13
상세설명  Digital Media System-on-Chip (DMSoC)
PDF  163 Pages
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TMS320DM355
SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010
www.ti.com
ID.
–
The RBL contains an internal table with a list of known NAND devices. Table 3-23 shows the
devices contained in the tables.
–
If the device ID is not found in the table, then the RBL use the fourth byte of the NAND to decode
this to obtain the necessary parameters.
•
Once a device ID is identified, the first 24 blocks of the NAND are read sequentially starting with page
0 with an offset of 512 bytes. The purpose of the read is to locate a magic number which will identify
the revision of the silicon. Table 3-24 contains magic numbers and their functions.
•
If a Compatibility mode magic number is read, then the device enters compatibility mode. In
compatibility mode, NAND layout is identical to that used in previous revisions of the silicon as shown
in Table 3-25. Only 512-byte small blocks and 2048-byte big blocks are supported.
•
If a Standard mode magic number is read, the NAND layout is as shown in Table 3-26: 512-bytes
small block and 2048- and 4096- big block devices are supported. 8192-block devices are also
supported. Note: At the time of production of this document revision, only 4096-block devices were
available for testing.
•
Once a magic number is identified, the User Boot Loader (UBL) is loaded from the NAND, stored to
internal RAM, and executed.
Table 3-23. NAND Devices in NAND Device ID Table
DEVICE ID
PAGES PER BLOCK
BYTES PER PAGE
BLOCK SHIFT VALUE
NUMBER OF ADDRESS
FOR ADDRESS
CYCLES
0xE3
16
512+16
12
3
0xE5
16
512+16
12
3
0xE6
16
512+16
12
3
0x39(1)
16
512+16
13
3
0x6B
16
512+16
13
3
0x73
32
512+16
13
3
0x33
32
512+16
13
3
0x75
32
512+16
13
3
0x35
32
512+16
13
3
0x43
32
512+16
13
4
0x45
32
512+16
13
4
0x53
32
512+16
13
4
0x55
32
512+16
13
4
0x76
32
512+16
13
4
0x36
32
512+16
13
4
0x79
32
512+16
13
4
0x71
32
512+16
13
4
0x46
32
512+16
13
4
0x56
32
512+16
13
4
0x74
32
512+16
13
4
0xF1
64
2048+64
22
4
0xA1
64
2048+64
22
4
0xAA
64
2048+64
22
5
0xDA
64
2048+64
22
5
0xAC
64
2048+64
22
5
0xDC
64
2048+64
22
5
0xB1
64
2048+64
22
5
0xC1
64
2048+64
22
5
(1)
Present only on silicon revision 1.1.
92
Detailed Device Description
Copyright © 2007–2010, Texas Instruments Incorporated
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