TMS320DM355CZCEA13 datasheet(103/163 Pages) TI1

103 / 163 page

TMS320DM355

www.ti.com

SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010

5.2

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals should transition between VIH and VIL (or between VIL and VIH) in a

monotonic manner.

5.3

Power Supplies

The power supplies of DM355 are summarized in Table 5-1.

Table 5-1. Power Supplies

Customer Tolerance Package

Chip Plane

Description

Comments

Board

Plane

Name

Supply

1.3 V

±5%

1.3 V

CVDD

Core VDD

VDDA_PLL1

PLL1 VDDA

VDDA_PLL2

PLL2 VDDA

VDDD13_USB

USB 1.3 V supply

VDDA13_USB

USB 1.3 V supply

3.3 V

±5%

3.3 V

VDD

IO VDD for LVCMOS

VDDSHV

VDD

IO VDD for MXI/O1

VDDSHV

VDD

IO VDD for MXI/O2

VDDSHV1

VDD

IO VDD for ISB DRVVBUS

VDDSHV2

VDDA33_DDRDLL

DDR DLL analog VDD

VDDA33_USB

Analog 3.3 V power USB PHY

VDDA33_USB_PLL

Common mode 3.3 V power for USB

PHY (PLL)

VDD

IO VDD for peripherals

3.3 V

±5%

3.3 V

VDD_VIN

IO VDD for VideoIN I/F

VDD_VOUT

IO VDD for VideoOUT I/F

1.8 V

±5%

1.8 V

VDD_DDR

1.8 V

±5%

1.8 V

VDDA18

Analog 1.8 V power

1.8 V

±5%

1.8 V

VDDA18_DAC

Place decoupling caps (0.1mF/10mf) close

to chip

0 V

n/a

0 V

VSS_MX1

Connect to external crystal capacitor

ground

0 V

n/a

0 V

VSS_MX2

Connect to external crystal capacitor

ground

0 V

n/a

0 V

VSS

Chip ground

USB ESD ground

ground

VSS

0 V

n/a

0 V

VSSA

ground

Keep separate from digital ground VSS

0 V

n/a

0 V

VSSA_PLL1

PLL1 VSSA

0 V

n/a

0 V

VSSA_PLL2

PLL2 VSSA

0 V

n/a

0 V

VSSA_DLL

DLL ground

0 V

n/a

0 V

VSS_USB

USB ground

VSSA13_USB

VSSA33_USB

VSSA33_USB_PLL

0 V

n/a

0 V

VSS_USB_REF

USB PHY reference ground

VSSREF

0 V

n/a

0 V

VSSA_DAC

DAC ground

Keep separate from digital ground VSS

VDDS*0.5

VDDS*0.5 VREFSSTL

DRR ref voltage

VDDS divided by 2, through board resistors

5 V

USB_VBUS

VBUS

Connect to external charge pump

DM355 Peripheral Information and Electrical Specifications

103

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