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TMS320DM641 데이터시트(PDF) 69 Page - Texas Instruments

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부품명 TMS320DM641
상세설명  Video/Imaging Fixed-Point Digital Signal Processors
PDF  171 Pages
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제조업체  TI [Texas Instruments]
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TMS320DM641 데이터시트(HTML) 69 Page - Texas Instruments

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Device Configurations
69
June 2003 − Revised August 2004
SPRS222C
2.1.2
Device Configuration at Device Reset
Table 2−2 describes the DM641/DM640 device configuration pins, which are set up via external
pullup/pulldown resistors through the specified EMIFA address bus pins (AEA[22:19]) and the
TOUT1/LENDIAN pin (all of which are latched during device reset).
Table 2−2. DM641/DM640 Device Configuration Pins
(TOUT1/LENDIAN, AEA[22:19], and TOUT0/MAC_EN)
CONFIGURATION
PIN
NO.
FUNCTIONAL DESCRIPTION
TOUT1/LENDIAN
B5
Device Endian mode (LEND)
0
–
System operates in Big Endian mode
1
− System operates in Little Endian mode (default)
AEA[22:21]
[U23,
V24]
Bootmode [1:0]
− Boot mode (AEA[22:21]):
00 – No boot (default mode)
01 − HPI [DM641 only]; Reserved [For DM640 device]
10 − Reserved
11 − EMIFA boot
AEA[20:19]
[V25,
V26]
EMIFA input clock select
Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 –
AECLKIN (default mode)
01 − CPU/4 Clock Rate
10 − CPU/6 Clock Rate
11 − Reserved
TOUT0/MAC_EN
C5
Peripheral Selection
1
− EMAC and MDIO enabled
0
− EMAC and MDIO disabled
2.2
Configurations After Reset
2.2.1
Peripheral Selection After Device Reset
Video Ports, McBSP1, McBSP0, McASP0, and I2C0
The DM641/DM640 device has designated registers for peripheral configuration (PERCFG), device status
(DEVSTAT), and JTAG identification (JTAGID). These registers are part of the Device Configuration module
and are mapped to a 4K block memory starting at 0x01B3F000. The CPU accesses these registers via the
CFGBUS.
The peripheral configuration register (PERCFG), allows the user to control the peripheral selection of the
Video Ports (VP0 and VP1 [DM641 only]) McBSP0, McBSP1, McASP0, and I2C0 peripherals. For more
detailed information on the PERCFG register control bits, see Figure 2−1 and Table 2−3.



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