TMS320DM641 datasheet(95/171 Pages) TI

95 / 171 page

Interrupt Sources and Interrupt Selector

June 2003 − Revised August 2004

SPRS222C

Table 4−7. DM641/DM640 DSP Interrupts (Continued)

CPU

INTERRUPT

NUMBER

INTERRUPT SOURCE

INTERRUPT

EVENT

SELECTOR

VALUE

(BINARY)

INTERRUPT

SELECTOR

CONTROL

−

11010

VPINT1

VP1 interrupt [DM641 Only]

−

11011

Reserved

Reserved. Do not use.

−

11100

AXINT0

McASP0 transmit interrupt

−

11101

ARINT0

McASP0 receive interrupt

−

11110 − 11111

Reserved

Reserved. Do not use.

† Interrupts INT_00 through INT_03 are non-maskable and fixed.

‡ Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields.

Table 4−7 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and

selection, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646).

4.5.2

Interrupts Peripheral Register Description(s)

Table 4−8. Interrupt Selector Registers (C64x)

HEX ADDRESS RANGE

ACRONYM

COMMENTS

019C 0000

MUXH

Interrupt multiplexer high

Selects which interrupts drive CPU

interrupts 10−15 (INT10−INT15)

019C 0004

MUXL

Interrupt multiplexer low

Selects which interrupts drive CPU

interrupts 4−9 (INT04−INT09)

019C 0008

EXTPOL

External interrupt polarity

Sets the polarity of the external

interrupts (EXT_INT4−EXT_INT7)

019C 000C − 019F FFFF

−

Reserved

4.5.3

External Interrupts Electrical Data/Timing

Table 4−9. Timing Requirements for External Interrupts† (see Figure 4−8)

NO.

−400

−500

−600

UNIT

MIN

MAX

tw(ILOW)

Width of the NMI interrupt pulse low

tw(ILOW)

Width of the EXT_INT interrupt pulse low

tw(IHIGH)

Width of the NMI interrupt pulse high

tw(IHIGH)

Width of the EXT_INT interrupt pulse high

† P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.

EXT_INTx, NMI

Figure 4−8. External/NMI Interrupt Timing

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