TMS320DM641 datasheet(106/171 Pages) TI

106 / 171 page

External Memory Interface (EMIIF)

106

June 2003 − Revised August 2004

SPRS222C

4.8.3

EMIF Electrical Data/Timing

4.8.3.1

Asynchronous Memory Timing

Table 4−22. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module†‡

(see Figure 4−17 and Figure 4−18)

NO.

−400

−500

−600

UNIT

MIN

MAX

tsu(EDV-AREH)

Setup time, AEDx valid before AARE high

6.5

th(AREH-EDV)

Hold time, AEDx valid after AARE high

tsu(ARDY-EKO1H)

Setup time, AARDY valid before AECLKOUTx high

th(EKO1H-ARDY)

Hold time, AARDY valid after AECLKOUTx high

† To ensure data setup time, simply program the strobe width wide enough. AARDY is internally synchronized. The AARDY signal is only

recognized two cycles before the end of the programmed strobe time and while AARDY is low, the strobe time is extended cycle-by-cycle. When

AARDY is recognized low, the end of the strobe time is two cycles after AARDY is recognized high. To use AARDY as an asynchronous input,

the pulse width of the AARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.

‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are

programmed via the EMIF CE space control registers.

Table 4−23. Switching Characteristics Over Recommended Operating Conditions for Asynchronous

Memory Cycles for EMIFA Module‡§¶ (see Figure 4−17 and Figure 4−18)

NO.

PARAMETER

−400

−500

−600

UNIT

MIN

MAX

tosu(SELV-AREL)

Output setup time, select signals valid to AARE low

RS * E − 1.5

toh(AREH-SELIV)

Output hold time, AARE high to select signals invalid

RH * E − 1.9

td(EKO1H-AREV)

Delay time, AECLKOUTx high to AARE valid

tosu(SELV-AWEL)

Output setup time, select signals valid to AAWE low

WS * E − 1.7

toh(AWEH-SELIV)

Output hold time, AAWE high to select signals invalid

WH * E − 2.5

td(EKO1H-AWEV)

Delay time, AECLKOUTx high to AAWE valid

1.3

7.1

‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are

programmed via the EMIF CE space control registers.

§ E = AECLKOUT1 period in ns for EMIFA

¶ Select signals for EMIFA include: ACEx, ABE[3:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[31:0].

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