TMS320VC5502 datasheet(37/189 Pages) TI

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3.1.5

Boot Configuration

3.2

Peripherals

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

The on-chip bootloader provides a way to transfer application code and tables from an external source to

the on-chip RAM at power up. The 5502 provides several options to download the code to accommodate

varying system requirements. These options include:

• Host-port interface (HPI) boot, both in multiplexed and non-multiplexed modes

• External memory boot (via EMIF) from 16-bit asynchronous memory

• Serial port boot (from McBSP0) with 16-bit element length

• SPI EPROM boot (from McBSP0) supporting EPROMs with 24-bit addresses

• I2C EPROM boot (from I2C) supporting EPROMs larger than 512K bits

• UART boot

• Direct execution (no boot) from 16- or 32-bit external asynchronous memory

The external pins BOOTM2, BOOTM1, and BOOTM0 select the boot configuration. The values of

BOOTM[2:0] are latched with the rising edge of the RESET input. BOOTM2 is shared with GPIO2,

BOOTM1 is shared with GPIO1, and BOOTM0 is shared with GPIO0.

The boot configurations available are summarized in Table 3-3.

Table 3-3. Boot Configuration Selection Via the BOOTM[2:0] Pins

BOOTM[2:0]

BOOT PROCESS

000

Direct execution from 16-bit external asynchronous memory

001

SPI EPROM boot

010

Serial port boot (from McBSP0)

011

External memory boot (via EMIF) from 16-bit asynchronous memory

100

Direct execution from 32-bit external asynchronous memory

101

HPI boot

110

I2C EPROM boot

111

UART boot

The 5502 includes the following on-chip peripherals:

• An external memory interface (EMIF) (1)

–

Supporting a 32-bit interface to asynchronous memory, SDRAM, and SBSRAM

• A host-port interface (HPI) (1)

–

Configurable to 8 bits (multiplexed mode) or 16 bits (non-multiplexed mode)

• A six-channel direct memory access (DMA) controller

• Three multichannel buffered serial ports (McBSPs)

• A programmable analog phase-locked loop (APLL) clock generator

• General-purpose I/O (GPIO) pins and a dedicated output pin (XF)

• Four timers

–

Two 64-bit general-purpose timers

–

A programmable watchdog timer

–

A DSP/BIOS timer

• An Inter-integrated Circuit (I2C) multi-master and slave interface

(1)

The 5502 can be configured as follows:

–

32-bit external memory interface with 8-bit (multiplexed) host-port interface

–

no external memory interface with 16-bit (non-multiplexed) host-port interface

Functional Overview

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