TMS320VC5502 datasheet(83/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 3-30. Peripheral IDLE Control Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15-14

Reserved

MISC

13(1)

R/W

MISC bit

•

MISC = 0:

Miscellaneous modules remain active when ISTR.PERIS = 1

and IDLE instruction is executed.

•

MISC = 1:

MIscellaneous module is disabled when ISTR.PERIS = 1 and

IDLE instruction is executed.

Miscellaneous modules include the XBSR, TIMEOUT Error Register,

XBCR, Timer Signal Selection Register, CLKOUT Select Register,

and Clock Mode Control Register.

EMIF

12(1)

R/W

EMIF bit

•

EMIF = 0:

EMIF module remains active when ISTR.PERIS = 1 and IDLE

instruction is executed.

•

EMIF = 1:

EMIF module is disabled when ISTR.PERIS = 1 and IDLE

instruction is executed.

BIOST

11(1)

R/W

BIOS timer bit

•

BIOST = 0:

DSP/BIOS timer remains active when ISTR.PERIS = 1 and the

IDLE instruction is executed.

•

BIOST = 1:

DSP/BIOS timer is disabled when ISTR.PERIS = 1 and the IDLE

instruction is executed.

WDT

10(1)

R/W

Watchdog timer bit

•

WDT = 0:

WDT remains active when ISTR.PERIS = 1 and the IDLE

instruction is executed.

•

WDT = 1:

WDT is disabled when ISTR.PERIS = 1 and the IDLE instruction

is executed.

PIO

9(1)

R/W

Parallel GPIO bit

•

PIO = 0:

Parallel GPIO remains active when ISTR.PERIS = 1 (ISTR.[3])

and the IDLE instruction is executed.

•

PIO = 1:

Parallel GPIO is disabled when ISTR.PERIS = 1 and the IDLE

instruction is executed.

URT

8(1)

R/W

UART bit

•

URT = 0:

UART remains active when ISTR.PERIS = 1 and the IDLE

instruction is executed.

•

URT = 1:

UART is disabled when ISTR.PERIS = 1 and the IDLE instruc-

tion is executed.

I2C

7(1)

R/W

I2C bit

•

I2C = 0:

I2C remains active when ISTR.PERIS = 1 and the IDLE

instruction is executed.

•

I2C = 1:

I2C is disabled when ISTR.PERIS = 1 and the IDLE instruction is

executed.

(1)

If the peripheral is already in IDLE, setting PERIS (bit 3 of ISTR) to 0 and executing the IDLE instruction will wake up all peripherals, and

PICR bit settings will be ignored. If PERIS = 1, executing the IDLE instruction will wake up the peripheral if the PICR bit is 0.

Functional Overview

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