TMS320VC5502 datasheet(54/189 Pages) TI

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3.10

System Clock Generator

OSC

X2/CLKIN

/1,/2,...,/32

x2, x3,

...,x15

PLL

Divider D1

SYSCLK1

(Fast Peripherals)

SYSCLK2

(Slow Peripherals)

(EMIF Internal Clock)

SYSCLK3

CLKOSEL

(CLKOUTSR[2:1])

CLKOUTDIS

(CLKOUTSR[0])

CLKOUT

CLKMD

(CLKMD[0])

GPIO4 at Reset = 0 −> CLKMD[0] = 0

GPIO4 at Reset = 1 −> CLKMD[0] = 1

/1,/2,/4

EMIF

ECLKOUT1

ECLKOUT2

ECLKIN

EMIFCLKS

PLLREF

GPIO4

at Reset

55x

Core

CK3SEL (CK3SEL[3:0])

OSCOUT

PLLEN

(PLLCSR[0])

Clock Generator

ENA

PWRDN

Divider D0

D0EN

(PLLDIV0[15])

OSCPWRDN

(PLLCSR[2])

ENA

PLLOUT

D1EN (PLLDIV1[15])

Divider D2

ENA

D2EN (PLLDIV2[15])

Divider D3

ENA

D3EN (PLLDIV3[15])

CLKOUT3

(DSP Core Clock)

/1,/2,/4

/1,/2,...,/32

ENA

Divider OD1

OD1EN

(OSCDIV1[15])

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

The TMS320VC5502 includes a flexible clock generator module consisting of a PLL and oscillator, with several dividers so that different clocks

may be generated for different parts of the system (i.e., 55x core, Fast Peripherals, Slow Peripherals, External Memory Interface). Figure 3-12

provides an overview of the system clock generator included in the 5502.

Figure 3-12. System Clock Generator

Functional Overview

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