TMS320VC5502 datasheet(40/189 Pages) TI

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3.3.3

Serial Port 2 Mux

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 3-5. TMS320VC5502 Routing of Host Port Mux Signals

PARALLEL/HOST PORT MUX MODE = 0

PARALLEL/HOST PORT MUX MODE = 1

(PGPIO)

(8-BIT HPI MULTIPLEXED)

Data Bus

HD[7:0]

PGPIO[43:36]

HPI.HD[7:0]

Control Bus

HC0

PGPIO44

HPI.HAS

HC1

PGPIO45

HPI.HBIL

The 5502 has three serial ports: McBSP0, McBSP1, and McBSP2, each of which has six signals. The

signals for McBSP0 and McBSP1 are directly routed to pins on the 5502. Four of the pins for McBSP2 are

multiplexed with two pins of the on-chip UART and two pins of the GPIO, the mode of the Serial Port 2

Mux determines which signals are routed to the 5502 pins.

The mode of the Serial Port 2 Mux is determined by the state of the GPIO7 pin at reset. If GPIO7 is low,

the UART is enabled and its RX and TX pins are routed to the SP1 and SP3 pins, respectively. The

GPIO3 and GPIO5 pins are routed to the SP0 and SP2 pins, respectively. In this mode, McBSP2 will be

disabled and any writes or reads to/from its registers will result in a bus error if the PERITOEN bit of the

Time-Out Control Register is set to 1.

If GPIO7 is high, McBSP2 will be enabled and its CLKX2, CLKR2, FSX2, and FSR2 signals will be routed

to the SP0, SP1, SP2, and SP3 pins, respectively. In this mode, the UART will be disabled and any writes

or reads to/from its registers will result in a bus error if the PERITOEN bit of the Time-Out Control Register

is set to 1. GPIO3 and GPIO5 will not be available during this mode of the Serial Port 2 Mux.

Table 3-6 lists the individual routing of the McBSP2, UART, and GPIO signals to the Serial Port 2 Mux

pins.

Table 3-6. TMS320VC5502 Routing of Serial Port 2 Mux Signals

SERIAL PORT 2 MUX MODE = 0

SERIAL PORT 2 MUX MODE = 1

SP0

GPIO3

CLKX2

SP1

UART.TX

CLKR2

SP2

GPIO5

FSX2

SP3

UART.RX

FSR2

Functional Overview

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