TMS320VC5502 datasheet(134/189 Pages) TI

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(A ) The waveform relationship of CLKIN to CLKOUT depends on the multiply and divide factors chosen for the APLL synthesis and on the system

clock selected to drive CLKOUT. The waveform relationship shown in this figure is intended to illustrate the timing parameters only and may

differ based on configuration.

CLKIN

CLKOUT

Bypass Mode

5.6.5

EMIF Clock Options

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Figure 5-4. External Multiply-by-N Clock Timings

Table 5-6 through Table 5-8 assume testing over recommended operating conditions (see Figure 5-5 through

Figure 5-7).

Table 5-6. EMIF Timing Requirements for ECLKIN

(1) (2)

VC5502-200

VC5502-300

NO.

UNIT

MIN

MAX

tc(EKI)

Cycle time, ECLKIN

16P

tw(EKIH)

Pulse duration, ECLKIN high

0.4 * tc(EKI)

tw(EKIL)

Pulse duration, ECLKIN low

0.4 * tc(EKI)

E10

tt(EKI)

Transition time, ECLKIN

(1)

P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.

(2)

The reference points for the rise and fall transitions are measured at VIL MAX and VIHMIN.

Table 5-7. EMIF Switching Characteristics for ECLKOUT1

(1) (2) (3)

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

tc(EKO1)

Cycle time, ECLKOUT1

E – 1

E + 1

tw(EKO1H)

Pulse duration, ECLKOUT1 high

EH – 1

EH + 1

tw(EKO1L)

Pulse duration, ECLKOUT1 low

EL – 1

EL + 1

tt(EKO1)

Transition time, ECLKOUT1

td(EKIH-EKO1H)

Delay time, ECLKIN high to ECLKOUT1 high

td(EKIL-EKO1L)

Delay time, ECLKIN low to ECLKOUT1 low

(1)

The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

(2)

E = the EMIF input clock (CPU clock, CPU/2 clock, or CPU/4 clock) period in ns for EMIF.

(3)

EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIF.

Specifications

134

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