TMS320VC5502 datasheet(140/189 Pages) TI

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ECLKOUTx

EMIF.CEx

(see Note A)

EMIF.BE[3:0]

EMIF.A[21:2]

EMIF.D[31:0]

EMIF.ARE/SADS/SDCAS/SRE

(see Note C)

EMIF.AOE/SOE/SDRAS

(see Note C)

EMIF.AWE/SWE/SDWE

(see Note C)

BE1

BE2

BE3

BE4

PS9

PS1

PS4

PS5

PS8

PS9

PS6

PS7

PS3

PS1

PS2

BE1

BE2

BE3

BE4

EA3

PS8

READ latency = 2

(see Note B)

The read latency and the length of EMIF.CEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIF CE

Secondary Control Registers (CEx_SC1, CEx_SC2). In the figure, SYNCRL = 2 and CEEXT = 0.

The following parameters are programmable via the EMIF CE Secondary Control Registers (CEx_SC1, CEx_SC2):

− Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency

− Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency

− EMIF.CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, EMIF.CEx goes inactive after the final command has

been issued (CEEXT = 0). For synchronous FIFO interface with glue, EMIF.CEx is active when EMIF.SOE is active (CEEXT = 1).

− Function of EMIF.SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, EMIF.SADS/SRE acts as EMIF.SADS with deselect

cycles (RENEN = 0). For FIFO interface, EMIF.SADS/SRE acts as EMIF.SRE with NO deselect cycles (RENEN = 1).

− Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2

EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, and EMIF.AWE/SWE/SDWE operate as EMIF.SADS/SRE, EMIF.SOE, and

EMIF.SWE, respectively, during programmable synchronous interface accesses.

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Figure 5-10. Programmable Synchronous Interface Read Timings (With Read Latency = 2)

140

Specifications

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