PM5347 datasheet(30/302 Pages) PMC

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PM5347 S/UNI-PLUS

DATA SHEET

PMC-941033

ISSUE 6

SATURN USER NETWORK INTERFACE PLUS

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

PIN DESCRIPTION

Pin Name

Type

No.

Function

RBYP

Input

153

The receive bypass (RBYP) input disables clock

recovery. If RBYP is high, RXD+/- is sampled on

the rising edge of RRCLK+/-. If RBYP is low, the

receive clock is recovered from the RXD+/- bit

stream. RBYP requires an external pull-down

resistor.

RXD+

RXD-

PECL

Input

135

136

The receive differential data inputs (RXD+, RXD-)

contain the NRZ bit serial receive stream. RXD+/-

is sampled on the rising edge of RRCLK+/- when

clock recovery is bypassed (the falling edge may

be used by reversing RRCLK+/-), otherwise the

receive clock is recovered from the RXD+/- bit

stream. Please refer to the Operation section for

a discussion of PECL interfacing issues.

RXDO+

RXDO-

Output

131

132

The receive differential data outputs (RXDO+,

RXDO-) are sliced versions of the RXD+ and

RXD- inputs. These outputs are provided to allow

decision feedback equalization (DFE) to correct

baseline wander. It is intended that these outputs

be low pass filtered and attenuated to create an

appropriate correction signal that is summed with

incoming data to recover the low frequency

components.

RRCLK+

RRCLK-

PECL

Input

142

143

The receive differential reference clock inputs

(RRCLK+, RRCLK-) must be a jitter-free 19.44

MHz or 6.48 MHz reference clock when clock

recovery is enabled. When clock recovery is

bypassed, RRCLK+/- is nominally a 155.52 MHz

or 51.84 MHz 50% duty cycle clock and provides

timing for the S/UNI-PLUS receive functions. In

this case, RXD+/- is sampled on the rising edge of

RRCLK+/-. Please refer to the Operation section

for a discussion of PECL interfacing issues.

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