PM5347 datasheet(72/302 Pages) PMC

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PM5347 S/UNI-PLUS

DATA SHEET

PMC-941033

ISSUE 6

SATURN USER NETWORK INTERFACE PLUS

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Figure 6

- HCS Verification State Diagram

DETECTION

MODE

ATM DELINEATION

SYNC STATE

CORRECTION

MODE

No Errors Detected

In M Cells

(Pass M Cell)

Apparent Multi-Bit Error

(Drop Cell)

Errors

Detected

(Drop Cell)

No Errors

Detected

(Pass Cell)

ALPHA

consecutive

incorrect HCS's

(To HUNT state)

DELTA

consecutive

correct HCS's

(From PRESYNC

state)

Single-Bit Error

(Correct Error

and Pass Cell)

No Errors Detected

(Pass Cell)

In normal operation, the HCS verification state machine remains in the

'Correction Mode' state. Incoming cells containing no HCS errors are passed to

the receive FIFO. Incoming single-bit errors are corrected, and the resulting cell

is passed to the FIFO. Upon detection of a single-bit error or a multi-bit error, the

state machine transitions to the 'Detection Mode' state. In this state,

programmable HCS error filtering is provided. The detection of any HCS error

causes the corresponding cell to be dropped. The state machine transitions back

to the 'Correction Mode' state when M (where M = 1, 2, 4, 8) cells are received

with correct HCSs. The Mth cell is not discarded.

Performance Monitor

The Performance Monitor consists of two 12-bit saturating HCS error event

counters and a 21-bit saturating receive cell counter. One of the counters

accumulates correctable HCS errors which are HCS single-bit errors detected

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