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STM32L081CB 데이터시트(PDF) 30 Page - STMicroelectronics

부품명 STM32L081CB
상세설명  Access line ultra-low-power 32-bit MCU ARM-based Cortex-M0, up to 192KB Flash, 20KB SRAM, 6KB EEPROM, ADC, AES
PDF  110 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STM32L081CB 데이터시트(HTML) 30 Page - STMicroelectronics

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Functional overview
STM32L081xx
30/110
DocID027513 Rev 4
3.16.2
Universal synchronous/asynchronous receiver transmitter (USART)
The four USART interfaces (USART1, USART2, USART4 and USART5) are able to
communicate at speeds of up to 4 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 driver enable (DE)
signals, multiprocessor communication mode, master synchronous communication and
single-wire half-duplex communication mode. USART1 and USART2 also support
SmartCard communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability, auto
baud rate feature and has a clock domain independent from the CPU clock, allowing to
wake up the MCU from Stop mode using baudrates up to 42 Kbaud.
All USART interfaces can be served by the DMA controller.
Table 11 for the supported modes and features of USART interfaces.
Fast Mode Plus with 20 mA output drive I/Os (up to 1
Mbit/s)
XX(2)
X
Independent clock
X
-
X
SMBus
X
-
X
Wakeup from STOP
X
-
X
1. X = supported.
2. See Table 14: STM32L081xxx pin definition on page 35 for the list of I/Os that feature Fast Mode Plus
capability
Table 10. STM32L081xx I2C implementation (continued)
I2C features(1)
I2C1
I2C2
I2C3
Table 11. USART implementation
USART modes/features(1)
1. X = supported.
USART1 and USART2 USART4 and USART5
Hardware flow control for modem
X
X
Continuous communication using DMA
X
X
Multiprocessor communication
X
X
Synchronous mode(2)
2. This mode allows using the USART as an SPI master.
XX
Smartcard mode
X
-
Single-wire half-duplex communication
X
X
IrDA SIR ENDEC block
X
-
LIN mode
X
-
Dual clock domain and wakeup from Stop mode
X
-
Receiver timeout interrupt
X
-
Modbus communication
X
-
Auto baud rate detection (4 modes)
X
-
Driver Enable
X
X



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